Design And Implementation Of High-Performance NICs Integrating CNN Inference Accelerators

With the advent of the era of big data,deep learning technology has become a major hot spot for artificial intelligence.It has shown tremendous advantages in image recognition,speech recognition,and natural language processing,and it is continuously developing and changing.Among them,convolutional neural networks(CNNs)are an important branch of deep learning networks and play an increasingly important role.Under the situation where deep learning technology is booming,the scale and data volume of the network are also increasing.Some new architectures need to be proposed to handle large-scale data quickly and efficiently.Common deep learning acceleration technologies include CPU acceleration technology,GPU cluster acceleration technology,FPGA acceleration technology,ASIC acceleration technology,and processing in memory technology.Compared with various acceleration techniques for deep learning applications,this thesis proposes the acceleration and implementation of CNN algorithm using FPGA acceleration technology.Based on previous research,this thesis presents a high performance network interface chip that integrates CNN reasoning accelerators.The host sends tasks to the FPGA accelerator through the PCIE interface.The accelerators distribute and process tasks through low-latency links.Finally,the calculation results are sent back to the host.Under the existing experimental environment,this article has realized the establishment of FPGA acceleration platform,the design and processing of hardware and software communication modules,and the integration of the CNN inference acceleration module..Through experimental testing,we verified the correctness of the prototype system's functionality and demonstrated its good scalability.