High Performance Network Packet Processing System On RISC-V

The processing ability of data plane is always the key factor restricting the development of SDN and NFV,and the research on how to improve the performance of general-purpose processor message processing has never been stopped.Although frameworks like DPDK and netmap has greatly improved the packet processing capability of X86 architecture,the performance still does not meet the needs of SDN and NFV.RISC-V is an open-source instruction set architecture(ISA)designed by the University of California,Berkeley.Processors using RISC-V ISA have higher performance,using lower power and taking smaller chip size.After years of development,RISC-V has a complete software development tool chain now,and there are many hardware SoC designs based on RISC-V ISA.RISC-V processors can integrate more cores under the same area because of the feature of taking smaller hardware resource,which is especially suit for the high parallel application like network packet processing.This paper firstly designs the RISC-V processor hardware,then using several optimization methods improves the network packet processing performance.These designs and optimization methods provide reference for research on message processing capability of general-purpose processor.In the hardware design,we implement a new I/O data path to reduce the memory access during the packet processing.I/O device exchange data with CPU through Cache no longer memory,which can improve the data exchange efficiency.In the software design,we use a ring structure to manage network packets.This structure supports zerocopy transfer of packets between interfaces,and it can also reduce the performance loss due to the data-copy.We also use linear,fixed size packet buffers that are preallocated when the device is opened,thus saving the cost of per-packet allocations and deallocations.Through the optimization designs on hardware and software,the system implemented in this paper uses about 100 CPU clock cycles to moving one packet between the wire and the application.And It is much better than X86 architecture in the aspects of system efficiency and chip footprint.This shows that RISC-V can provide a new choice for packet processing in data plane.