Research On Implementation And Application Of Processor Instruction Level Pseudo Random Excitation Generator Technology

With the rise of the integrated circuit industry and the continuous development of technology,processor verification is an indispensable part of processor research and development.At present,the mainstream method for processor verification in the industry is still simulation verification technology based on pseudo-random testing.The most critical technology of this verification method is how to generate a large number of effective test stimuli in the least time.Therefore,the processor pseudo-random stimulus generator is the core key technology of simulation verification technology.Processor design verification must be one of the key technologies that can be controlled independently.The work of this paper is as follows:This article first analyzes the requirements for the development of pseudo-random excitation generators from two aspects,namely the requirements of processor function verification and the requirements of simulation environment.And by introducing the composition structure of IBM pseudo-random excitation generator,Loongson pseudo-random excitation generation environment and Shenwei-1 pseudo-random excitation generator,comparative analysis and example analysis are carried out to get a solution to the demand,and based on model and test knowledge The library's pseudo-random excitation generator.This paper proposes a model-based knowledge generator(KIG)with a rich knowledge base,which is a new generation of pseudo-random excitation generator.From the aspects of instruction tree implementation,structural model,test knowledge base,etc.,the composition of KIG is studied in detail,and the application of KIG is compared with the ordinary pseudo-random excitation generator.It is found that the existing KIG can quickly respond to the processor architecture and microstructure And changes to the instruction set.Since the existing KIG verification environment cannot meet the verification requirements of dual-thread architecture processors,this article will improve and optimize the original KIG.First,the micro-structure of the dual-thread processor X is introduced in detail.Through the development of the processor structure,the pipeline change,and the memory access pipeline requirements,a dual-thread instruction is randomly generated.The scheme proposes an improved modeling method for the original KIG's memory access address structure—dual threads distinguish the thread numbers by different address bits when sharing memory access addresses and private memory access addresses.Thread processor X is used in the verification work,and then the correctness is verified according to the function point of the dual-thread processor X,so that the function coverage can reach 100%.