Research And Hardware Design Of Image Denoising Algorithm Based On CMOS Image Sensors

In the recent years,the performance of CMOS image sensor has surpassed the traditional CCD image sensor due to its low power consumption and low manufacturing cost.However,the CMOS image sensor still suffers from image noise,limiting its overall accuracy.Therefore,in my dissertation,I have devoted my time to research on noise suppression for CMOS image sensors.In the first part of my dissertation,to address the two main noise sources(Gaussian noise and salt and pepper noise),I have evaluated the performance of four classic image denoising algorithms.Mean filtering and median filtering are typical algorithms.Guided filtering and wavelet transform denoising algorithms are optimized for “edge preservation” problem which minimize image blurring at the image boundary.The peak signal-to-noise ratio(PSNR)and structural similarity(SSIM)were used as the evaluation standards to study the effects of these algorithms in dealing with different noises.To address the salt and pepper noise,the denoising effect of the guided filtering algorithm has shown better performance than the wavelet denoising algorithm.To address the Gaussian noise,the guided filtering algorithm has shown better performance than the mean filtering and median filtering algorithms.Based on the various factors such as denoising quality and circuit implementation difficulty,the guided filter algorithm was selected to realize its hardware design and applied to the system of CMOS image sensor.Therefore,in my dissertation,I have selected the guided filtering algorithm as the image process block of the CMOS image sensor and implemented in ASIC design and validated the algorithm in FPGA board.In order to maximize the usage rate of memory access bandwidth,a dual-module parallel processing method was proposed based on the eight-channel data transmission.HL55 lp process was applied in the design compiler of the proposed guiding filter hardware module.The total amount of the on-chip memory occupied by this module is 46.875 KB.The highest clock frequency is 120 MHz and the pixels number processed per line by the module can reach 4800.The module possesses a high processing rate of 196 M pixels/second.