Research Of SCMA Low Hardware Complexity Expectation Propagation Algorithm Based On Approximate Computing

Sparse code multiple access(SCMA)is one of the promising non-orthogonal multiple access(NOMA)techniques for the future mobile communication systems,which can provide three times the connections of the orthogonal multiple access(OMA)techniques.Thus,SCMA can meet the demand of massive connections in the future mobile communication systems commendably.However,the complexity of the optimal decoding algorithm,message passing algorithm(MPA),is exponential to the codebook size and the signal superposition degree,which can hardly be applied in the practical systems because of the extremely high complexity.Expectation propagation algorithm(EPA)is another kind of SCMA decoding algorithm,which can decrease the complexity of MPA substantially while keeping the same decoding performance.But there are a large amount of non-linear,multiplication and division operations in EPA.It will bring the problem of high hardware logic overhead and long critical path delay,which is a great challenge for hardware implementation.In order to reduce the high hardware implementation complexity of the traditional SCMA decoding algorithms,two low hardware implementation complexity algorithms based on approximate computing are proposed in this thesis.The main innovations of this thesis are as follows:1.A max-log approximation based expectation propagation algorithm(Max-log EPA) is proposed in this thesis.In view of many complex operations in EPA,Jacobi logarithm approximation and the variance relationship are utilized to derive the Max-log EPA.Three approximation methods to reduce the complexity of EPA at the variable node,the function node and the LLR calculation are presented. Performance simulation and statistical results show that Max-log EPA can reduce 32.1% complexity of EPA with only 0.1dB performance loss,and bring higher complexity reduction gain when the higher order codebook is adopted.2.A stochastic computing based expectation propagation algorithm(Stochastic EPA) is proposed in this thesis.In order to reduce the hardware implementation complexity of EPA,stochastic computing is applied into the variable node,which is the most complicated computation node in EPA.The original complex calculation units are replaced by the simple stochastic logic units.Stochastic EPA is obtained by combining the approximation method for the function node and the LLR calculation.Performance simulation and statistical results show that Stochastic EPA can reduce 35.1% complexity of EPA with only 0.3dB performance loss,and bring higher complexity reduction gain when the lower order codebook is adopted.3.Stochastic EPA is implemented in hardware in this thesis.The FPGA hardware architecture of the Stochastic EPA decoder is designed,and an interleaved pipeline structure is proposed,which can improve the throughput and the hardware efficiency. Performance simulation and implementation results show that the Stochastic EPA decoder can improve 54.6% hardware efficiency of the Stochastic MPA decoder with 0.4dB performance gain.