Research On Image Stitching Acceleration Based On SIFT Algorithm

Image stitching technology can obtain wide viewing angle and high-resolution images,which is one of the research hotspots in the field of computer vision.There are a wide range of image stitching applications,including drone aerial photography,3D reconstruction,remote sensing images,virtual reality,etc.Image stitching refers to spatially registering a series of images with overlapping regions of two or more images and then splicing into an image containing all the information of the original image sequence.Image stitching technology mainly includes two parts,image registration and image fusion.In the field of image registration,SIFT algorithm is one of the best comprehensive performance algorithms,but its algorithm steps are complex and computationally intensive,and it is difficult to meet the requirements of real-time.In the field of image fusion,Alpha fusion has a small amount of computation and a significant fusion effect,and has been widely used.In addition,today's image acquisition devices have high resolution,and high-resolution raw images put a lot of pressure on subsequent image processing.In image stitching,how to speed up algorithm calculation becomes the bottleneck of its application.In order to solve the above problems,this paper designs an image mosaic acceleration system based on SoPC.SoPC has an ARM+FPGA architecture that combines the advantages of software processing and programmable hardware for a more flexible design.On Xilinx's Zynq 7020 platform,the software splicing system is divided into software and hardware,and the complicated process control is completed by software.A large amount of image processing is transferred to the FPGA for parallel computing,which greatly accelerates the process of image splicing.In the aspect of algorithm optimization,the high-resolution image is compressed by wavelet transform to extract its low-frequency components.The Gaussian pyramid of SIFT algorithm is processed in parallel,the Gaussian template is split and fixed,the CORDIC algorithm is used to calculate the gradient data,the square template of descriptor is changed to a circular template,and the template is obtained by the optimization method.In digital logic design,space parallelism and pipeline design are used as much as possible to reduce time consumption,shared cache,in-place computation,use of register sets instead of multivariable assignments,and use of lookup tables to reduce the consumption of logic resources.In the software,the solution of the homographic matrix,image mapping,image fusion and result display are realized.After software model simulation,software and hardware module writing,digital time series simulation,the system comprehensive performance test,the system has good scale invariance,rotation invariance,translation and illumination invariance and certain affine invariance,the fusion effect satisfies the vision The hardware matching time is within 30 ms,and the entire splicing process is within 300 ms,and the acceleration effect is remarkable.