Design And Implementation Of Clos High-speed Switching Network Based On AXIS

Nowadays,with the rapid development of information technology,the integration degree and manufacturing technology of integrated circuits have been improved accordingly.Moreover,by the quick update of computer and communication technology,the new generation of bus protocol standards has emerged one after another.The evolutions in these technical fields have greatly improved the functions,performance and data throughput of the current signal processing platforms as well as of the information and communication equipments.As an indispensible part of connecting nodes in all kinds of the communication and signal processing platform equipments,the switch network is facing new challenges,including the throughput,delay,power consumption,complexity and so on.Based on the research background and project requirements,this thesis studies and designs a three-stage Clos high-speed switching network.The system is based on the AXI4 bus protocol for Ethernet data packet switching services.And it aims to achieve the goals of high capacity,low power consumption,fault tolerance,and low complexity.This thesis tends to complete the goal in terms of the following aspects:First of all,a variety of classic switching structures of single-stage switching and multi-stage switching are studied.And the advantages and disadvantages are compared with the analysis of their unique structural characteristics.In addition,several scheduling algorithms which are generally mature and widely used are also studied,which lays a foundation for the follow-up scheduling algorithm design in this thesis.Secondly,based on the MSM(Memory-Space-Memory)three-stage Clos structure,the overall structure of data switch and the arbitration scheduler are designed.And this thesis mainly optimizes the design and implementation of functional modules such as MAC address extraction,port mapping management,arbitration scheduler and so on.In particular,an asynchronous orthogonal scheduling mechanism is innovatively proposed,which can avoid waste of bandwidth resources caused by fixed-length cell cutting.The improvement will effectively improve the performance of the system.Thirdly,a series of innovative optimization designs are carried on the power consumption,fault tolerance and other aspects of the system.Multiplexing compression coding is designed for AXI4 protocol,and clock gating management is also added to each sub-switch module of the Clos switch to achieve the purpose of saving hardware resources and reducing power consumption.By making use of the characteristics of the multi-channel path of the Clos switch,a flexible fault-tolerant design is realized.In addition,in order to reduce the scheduling delay caused by the asynchronous scheduling mechanism,a prefetch design is used in the scheduler to realize the scheduling pipeline and reduce the delay.Finally,with the help of simulation tools and verification methodology,the timing and functions of the system were tested,verified,and corrected at the module level and the system level,respectively.The test results show that the timing and the function of each module of the system meets the design expectations.And the data switch can work normally under heavy load.