Research And Design Of High Precision ?? Modulator

In recent years,with the rapid rise of integrated circuit technology and the rapid development of digital signal processing technology.Analog signals such as bioelectronic signals in biomedical applications,audio signals in life,and signals detected by precision instruments need to be converted into reliable digital signals for further processing.Because these signals have large amplitude fluctuation range and low frequency,the general front end needs a controllable gain amplifier,and then cascades the high-precision analog-to-digital converter(ADC)to collect information on the signal.Techniques such as oversampling,noise shaping,and decimation filtering of discrete-time ?? ADCs enable higher precision analog-to-digital conversion and wider dynamic range,Moreover,the ?? ADC with discrete time structure is easy to integrate,and the performance is superior,which can achieve high precision.Therefore,??ADC is a research hotspot in recent years.This subject is based on high-precision discrete-time ?? ADC.Since the output performance of the ?? ADC is mainly determined by the ?? modulator,a high-precision discrete-time ?? modulator is designed.Its main work is as follows:(1)Using the structure of the third-order one-bit quantization cascade feedforward discrete-time modulator,the limiting model of the modulator is established in the simulink environment of Matlab software,and the loop stability of the modulator is considered.At the same time,the non-ideal factors of the circuit are modeled and analyzed,including sampling switch noise,equivalent noise of the op amp,clock jitter,slew rate of the op amp,gain bandwidth product of the op amp,and DC finite gain of the op amp.And other factors.Under the condition of combining the above non-ideal factors,the output effective precision of the modulator model is 19.67 bits.(2)Next,the TSMC 0.18?m CMOS process was used to design the modulator circuit under the condition of 3.3V power supply voltage.The gain of the op amp is improved by using the gain bootstrap technique to eliminate the effects of the dead zone effect.Switching chopping technology is used to remove the 1/f noise and offset of the integrator,optimizing circuit noise performance.A common mode feedback technique is used to stabilize the integrator DC operating point.At the same time,a pre-amplified regenerative latching comparator is designed,which eliminates the comparator kickback noise by the input stagecapacitor compensation method,thereby improving the output accuracy of the modulator.The pre-simulation result of the final modulator circuit shows that the output signal-to-noise ratio of the modulator circuit is at the clock frequency of 16.384 MHz,oversampling of 128 times,sampling rate of 128kS/s,input signal frequency of 14 kHz,and signal Vpp of 2.2V.98.1dB,corresponding to an effective precision of 16.00 bits,the entire modulator consumes15.98 mW.(3)Finally,the layout of the overall modulator circuit is drawn and post-simulation is performed,in which the core area of the layout is 430?m×180?m.Compared with the pre-simulation,when the modulator input signal frequency is 30 kHz,the output signal-to-noise ratio of the modulator is 96.2 dB,and the corresponding effective precision is15.69 bits.