Acceleration And Optimization Of P4 Software Switch Based On DPDK

Emerging network technologies are emerging one after another.With the development of such as 5G networks,Internet of Things and Internet of Vehicles,the demand for customized packet processing behavior is increasing.However,due to problems such as the high coupling of software and hardware and the diversity of management interfaces,traditional switches are difficult to solve the problems caused by such new technologies.SDN(Software Defined Network)and P4(Programming Protocol-Independent Packet Processors)protocols have been proposed so that the switch can easily support network innovation.Many scholars have studied the P4 switch and proposed a variety of P4 switches.However,these P4 switches have certain shortcomings or deficiencies.For example,P4 switches based on hardware platforms have high performance but lack portability.P4 switches based on X86 architecture software platforms have high portability but lack support for P4 protocol or the forwarding speed is slow.It can be seen that the optimization and acceleration of P4 switches is an important research topic in the development of the data plane.So,this paper proposes a two-layer architecture acceleration optimization scheme for BMv2(Behavioral Model Version 2,P4 software switch provided by P4 Language Alliance),using the DPDK(Data Plane Development Kit).The main work of this paper includes the following three parts:(1)After deeply studying the program structure of the switch,redesign it and propose a two-layer architecture program model.In order to reduce the amount of unnecessary development,the original program classes are hierarchically classified and classified into the upper layer of the architecture or the lower layer of the architecture.(2)The P4 language data packet processing model is implemented on the upper layer of the architecture.In the acceleration optimization,the lock queue of the switch is accelerated and optimized.The lock queue is optimized as a lock-free circular queue,which doubles the queue performance.(3)The lower layer of the architecture uses the data plane acceleration development kit to implement high-speed data message transmission and reception,and shields the underlying hardware from the upper layer.In the acceleration optimization,the initialization function of the data plane acceleration development kit,the multi-thread data message polling,sending and receiving,and data message changing functions are implemented,and the relevant code is compiled into a dynamic link library(DLL).The link library is encapsulated into classes and provides Application Programming Interface(API)to the upper layer of the architecture.Finally,this paper tests and compares the performance of the original P4 switch and the accelerated P4 switch.In the performance test,use the Packet Internet Groper(PING)to test the end-to-end delay of the switch first,and then use the pktgen-dpdk(a dedicated network test suite)to test the throughput of the two switches in three network bandwidth test scenarios.Experimental test results show that the accelerated P4 switch's end-to-end delay is reduced.In the three test scenarios,the 64-bytes data packet forwarding performance has reached 1000 Mbps,compared with the original P4 switch,the delay performance is improved by three times,and the throughput has increased by 11 times.