The Design And Study Of Reconfigurable RF Front-end Power Amplifier Integrated With Filter

In the past 20 years,wireless technology applications have shown explosive growth.The development of multiple cellular standards has different requirements for the output power and linearity of the RF front-end.Whether the RF front-end can achieve high efficiency,miniaturization,and low power consumption has become the key factors to occupy the market.Integrating different RF front-end devices on the same chip for collaborative design can reduce the number of devices and reduce the size and cost of the system.By integrating the matching circuit and index performance of discrete components,you can reduce losses and improve efficiency.Since it can adapt to a variety of different communication systems,the multifrequency and multi-mode reconfigurable RF front-ends will become mainstream in the future when multi-communication systems are becoming universal.Based on the reconfigurable multi-frequency multi-mode radio frequency power amplifier(MMPA)chip in the different frequency bands of 4G LTE,this article integrates a surface acoustic wave(SAW)filter on the substrate inside the chip.This reduces the number of components in the RF front-end,the size and quality of the entire system,and reduces costs.The system design on the entire chip substrate consists of MMPA's driver stage,amplifier stage,switch,SAW filter and matching circuit.Because MMPA is a narrow-band adjustable PA,it can be switched to different frequency bands through switches,so it is possible to match two or more SAW filters in different frequency bands to the corresponding RF transmission path.In order to realize the integration of the characteristics and functions of the MMPA and SAW filters at the interface port in collaborative design,the impedance matching principle is used to design and debug the matching circuit between the PA and SAW filters to achieve the linearity,output power and efficiency required by the product index.At the same time,in the process of drawing the substrate,use layout design principles and electromagnetic compatibility principles to ensure symmetry as much as possible,reduce process deviation and ohmic contact mismatch,and prevent mutual interaction between PA,SAW filters and RF path signal lines during layout placement and routing to achieve ideal matching integrated design performance.After the chip is taped out,test the chip and debug the matching circuit on the substrate to achieve more optimized performance indicators.At the same time,a series of reliability tests such as electrostatic discharge test(ESD),high temperature working life test(HTOL),temperature cycle test(TCT)and non-biased highly accelerated temperature and humidity stress test(u HAST)are performed to verify the chip design and packaging reliability impact.The test results of the chip show that compared to the discrete chip,the EUTRA in the adjacent channel leakage ratio(ACLR)is optimized by 0.54 d Bc,UTRA is optimized by 1.33 d Bc,the efficiency PAE is increased by 0.55%,and the gain is increased by 0.32 d B.Reliability static test and aging test meet production requirements.