Optimization And Hardware Implementation Of Convolutional Code Neural Network Decoding Algorithm

As an important type of error correction code,convolutional codes are widely used in various communication systems.Neural networks have demonstrated excellent capabilities in various fields,and the application of neural networks to the decoding process of convolutional codes has also attracted a lot of research.Based on the convolutional code neural network decoding algorithm proposed by our laboratory,research on algorithm optimization and hardware implementation is carried out in this thesis.Mainly carried out the following work:(1)On the basis of the convolutional code neural network decoding algorithm proposed in our laboratory,three integrated decoding schemes are proposed,which reduce the bit error rate by at least 10%,and with the increase of the signal-to-noise ratio,the ratio of the bit error rate decreases shows an increasing trend;by optimizing the integration length,the decoding throughput rate is doubled.(2)The neural network in the neural network decoding algorithm is compressed.Among them,the neural network parameters are reduced by 98% by cutting the neural network;the quantization bit width of the neural network decoder is reduced to 8 bits by the quantization scheme design.(3)The neural network decoding algorithm is implemented in hardware.According to different considerations on decoding throughput and decoding performance,three neural network decoders that meet different requirements are realized,and through parameterized design,a neural network decoder compatible with multiple decoding window lengths and multiple parallelisms is realized;And based on Modelsim,the functional simulation of the neural network decoder implemented in this thesis was carried out,and its decoding performance was verified;Finally,the neural network decoding algorithm was synthesized,placed and routed based on Quaturs II in Stratix IV-EP4SGX230KF40C2.