Analysis And Design Of Monobit Quantization Link

With the continuous development of modern wireless communication systems towards large bandwidths and high rates,the processing power consumption of highprecision analog-to-digital converters(ADCs)in the system is also increasing.The high power consumption and massive data processing brought by the high-precision ADC are a bottleneck problem which restricting the development of communication system.Reducing ADC power consumption has become an important subject in the field of highspeed communication.Due to the exponential relationship between ADC power consumption and quantization accuracy,reducing ADC precision is a direct option to reduce system power consumption.And as the transmission frequency band continues to increase,the available bandwidth of the link also increases.In order to cope with the attenuation during high-frequency carrier transmission,MIMO,directional antenna and other methods are used to increase the spatial directivity,which further reduces the spectral efficiency requirements of the link,and the link bandwidth index is no longer strict.When the channel conditions are stable,high-precision ADC is no longer necessary.The concept of low precision quantization represented by monobit quantization came into being,and the monobit quantization theory and design of the receivers have become a new research direction.Faced with the actual demand of modern wireless communication systems to increase the signal transmission rate while increasing power efficiency,this paper analyzes and studies the implementation scheme of monobit quantization link.In-depth research work has been carried out from the application scenarios of monobit quantization receiving technology,index requirements,key problems to be solved in the process of building the chain,non-ideal factors in the link,algorithm scheme of the link transceiver,etc.The main work and research results are as follows:The application scenarios and indexes of monobit quantization link are analyzed,and the index requirements of the link to realize point-to-point communication are proposed.The modulation mode required in this paper is Quadrature Phase Shift Keying,which is commonly used in communication systems.The transmission rate is not less than 2Gsps.The digital processing part is realized based on FPGA.Starting from the low-cost design concept and high-speed and high-bandwidth link conditions,the overall architecture of the transceiver is determined.The transmitter chose a simple rectangular 2PAM signal shaping method,which avoids the huge amount of data processing brought by digital shaping filtering at high transmission rate,and reduces the cost and power consumption of the analog-to-digital conversion process.At the receiving end,based on the waveform characteristics of complete loss of the monobit quantized signal amplitude information,a receiver scheme is proposed,which uses a low-pass filter receiving system to obtain four baseband signals from two channels of I and Q receiving signals through linear operation,and then carries out monobit quantization,high-speed transceiver sampling and sending them to FPGA for digital processing.This paper analyzes the key problems of the link from the perspective of receiver's realization,and points out that the carrier synchronization and timing synchronization at the receiver are the key problems to be solved in the link.Combined with the waveform characteristics of the monobit received signal,an in-depth theoretical analysis of the carrier synchronization and timing synchronization is carried out respectively,and the concept of phase quantization that divides the phase deviation into 8 intervals is proposed.The waveform of the signal is analyzed under different frequency offsets and different timing offsets,and a carrier synchronization scheme based on loose tail ring is proposed according to the actual characteristics and changing rules of the signal.Aiming at the device function of Xilinx 7 series FPGA and the actual link structure framework,it is proposed to use the built-in high-speed transceiver in the FPGA for timing synchronization.Aiming at the impact of non-ideal factors in link transmission,the impact of IQ imbalance,noise,and clock drift on receiver performance are mainly studied.Through theoretical analysis and simulation verification,the carrier synchronization and timing synchronization scheme of the link is determined,and a link transmission protocol is proposed combining the non-ideal factors in the actual link.