Design And Research Of ECC Binary Field Width Adjustable System Based On FPGA

Elliptic Curve Cryptography(ECC)is now a popular public key cryptosgraphy.ECC can be implemented by hardware or software.Hardware implementation has higher security and faster operation speed than software implementation.Field-programmable gate array(FPGA)is a popular chip for hardware design and development.This thesis is based on FPGA ECC binary field width adjustable system design,which can adjust the curve of field width n=163,233,283 in Koblitz curve recommended by NIST.verification.This article mainly carries out the following research work:(1)Introduce the relevant theoretical basis of ECC,and design the structural hierarchy of the adjustable field width ECC system according to the theoretical basis.(2)Analyze and improve algorithms at all levels of the ECC system.(3)Design the hardware architecture of the ECC system according to the improved algorithm and divide the modules.(4)Hardware implementation of each module of ECC system;This thesis has made some innovations and improvements in the realization of ECC point multiplication arithmetic module,modular multiplication arithmetic module and ECC field width adjustable system.The point multiplication operation on the elliptic curve uses the Montgomery algorithm in the Lopez & Dahab projected coordinate system.Modular multiplication algorithm of the core operation in the binary field adopts a modified serial-parallel algorithm.The modular inversion operation is implemented by disassembling the modular inversion into modular multiplication and modular squarer operations according to Fermat's little theorem.Finally,using the Verilog HDL language to design the RTL code of each module of the ECC system on the Vivado 2017.4 software,using Vivado Simulator to complete the functional simulation,and verify the ECC digital signature results on the Xilinx Artix-7 series FPGA development board.According to the timing analysis results of the point multiplication module,when the domain width n = 233 is selected,the minimum clock period of the point multiplication operation is 6.595 ns,and the maximum clock frequency is 151.63 MHz.Compared with other similar literature,the calculation efficiency is improved.Figure [32] table [6] reference [42]...