Study On Reliability Of Charge-trapping 3D NAND Flash

NAND flash memories are widely used for data storage with the continuous improvement of storage density and reliability.Due to process technology and physical limitations,when the size of two-dimensional NAND(2D NAND)flash memory is developed to 15nm,flash memory chips cannot further increase the integration density without preserving storage reliability.Now,with the flash memory technology spanning from a plane to a three-dimensional stack(3D NAND)architecture,3D NAND flash memory technology has shown many advantages over 2D NAND flash memory.But due to its device structure and preparation process,there are reliability issues different from 2D NAND flash.3D NAND flash memory includes two types of charge-trapping and floating gate.This paper focuses on the reliability analysis of charge-trapping 3D NAND flash memory and proposes targeted improvements..The first part of this paper is to analyze the reliability of charge-trapping 3D NAND flash memory at room temperature.First,it is found that the error rate degradation during program/erase(P/E)cycling is dominated by the least significant bit(LSB)page,where 1 to 0 is the major contribution.With a further study on error bit distributions as a function of the program page number,four distinct distribution regions are identified in the case of LSB page.Secondly,with a study on memory cells of different programming levels,it was found that after repeated P/E cycles,data retention is performed,the positive shift of the threshold voltage gradually becomes the main source of error rate.These can be well explained in considering of P/E stress induced shallow traps generation,P/E cycling enhanced lateral charge diffusion in charge-trapping 3D NAND flash memory.Thirdly,by using proposed pre-charging scheme,over 30%error rate are successfully suppressed in data retention no matter at the fresh state or after P/E cycling.In addition,data retention correlated abnormal read disturb has been systematically investigated in charge-trapping 3D NAND flash memory,read disturb will cause more error bits after programming,however,after short-time retention,read disturb has weak effects on the error bits during read,more importantly,after long-time retention,part of error bits even can be corrected by read disturb on the contrary,which has never been observed before in 2D NAND memory With designed coding approach,it is found that lateral charge migration in the common charge-trapping layer is the dominant mechanism.This phenomenon can be utilized to prolong the lifetime of 3D NAND based memory system for cold storage applications.The second part of this paper is to analyze the reliability of charge-trapping 3D NAND flash memory under high temperature conditions.First,the effect of high-temperature baking under different storage states,which is,the effect of different states of the memory cell before baking on the next program data is studied,and it is found that when the cell is in the programming state,the data retention for the next program data better.The specific reason is that during the high-temperature baking of the device,the electrons in the memory cell move to the space charge region due to the lateral diffusion effect.When the data is programmed next time,the electrons in the space charge region suppress the electron loss in the memory cell.Second,the effect of high temperature annealing on the worn 3D NAND flash memory devices is analyzed,memory cells are partly recovered when baking at the erase state.