Research Of H.264 Fast Video Encoding Algorithm Based On TMS320DM8168

With the rapid development of communication technology,video has gradually become one of the main ways of transmitting information for humans.At the same time,a lot of video information puts tremendous pressure on network transmission and video storage.Due to the efficient coding efficiency of the H.264 coding standard,it has been widely used in the field of video coding and decoding.But in some fields,such as video conferencing,telemedicine,video guidance,the delay requirement for video is particularly high,which makes the research of H.264 fast video encoding algorithm more and more important.The development of video codec system is a very large and complex project.In order to shorten the development cycle of H.264 fast coding algorithm research,and to reduce the design complexity and design workload,and to ensure better real-time requirements,we adopt TMS320DM8168 which is a high-performance processor chip for video codec and is designed by Texas Instruments,and designs one hardware system,and also uses development kit named DVR-RDK released by Texas Instruments to realize video acquisition,video encoding and video network transmission based on RTP protocol,and use VLC for decoding and display.Based on the video codec system mentioned above,we one by one analyze many links from acquisition to decoding,and clarify the source of the delay,and specifically reduce the delay of the entire video codec system.In this paper,we mainly use the following methods to reduce the delay of the entire video codec system.Firstly,Combining the multi-core architecture of TMS320DM8168,the algorithm of parallel processing based on frame layer is proposed,which ensure that tasks such as acquisition,encoding and network transmission can run simultaneously in parallel on multiple cores.Therefore,encoding efficiency is critically improved and system latency is reduced effectively.Secondly,in order to reduce the buffer latency,in this thesis,we use CBR rate control to smooth the encoded bit stream.Thirdly,we adopt all-I frame structure for encoding.on the one hand,the frame structure can reduce the delay caused by B-frame bidirectional prediction or frame reordering.on the other hand,the frame structure can effectively smooth the encoded bit stream fluctuation,and reduce the buffer latency.Fourthly,aiming at the frame structure of IPPP...,a single direction forced intra refresh algorithm is proposed.The basic idea of the algorithm is to split image into M equal-sized vertical strips,and to sequentially refresh each vertical strip from left to right,that is to force intra prediction encoding for each vertical strip.This results in a complete intra refresh after M frames.On the time of the video transmission,the I frame is discarded,and only the P frame behind the I frame is transmitted,and the image can be restored by the vertical stripe of the forced refresh when decoding.This way not only keep the efficient coding efficiency of the IP frame structure but also significantly smoothes the encoded bit stream fluctuation,greatly reducing the encoder buffer sizes,thus effectively reduces the buffer delay.Finally,we design a complete video codec test system,and systematically test the proposed algorithm.The test results show that under the premise of ensuring good subjective quality and stability of the video,the total delay of the system is within 300 ms,which meets the design requirements.