Research And Implementation Of Time Sensitive Network Exchange Scheduling Mechanism

Time Sensitive Network(TSN)guarantees the real-time and reliability of data transmission with a series of critical techniques,such as high-precision time synchronization,resource reservation,path control,traffic shaping and scheduling and etc.These features assure TSN an important place in the fields of professional audio and video distribution,autonomous driving,industrial control,aerospace and so on.In this thesis we study the key scheduling technologies in TSN,propose a design scheme of the TSN switch scheduling system based on an FPGA platform,with a focus on the design and implementation of the Scheduling module.Firstly,we study the key technologies in TSN,and analyze the IEEE 802.1Qav protocol and IEEE 802.1Qbv protocol relevant to the packet scheduling,including priority mapping and the CBS algorithm in Qav protocol,and gated scheduling scheme in Qbv protocol.Among them,the application background,basic principles and related parameters of each technology are investigated.On the basis of that,a design scheme of TSN switch scheduling system is proposed.The system supports the functions of processing of SRP frame and g PTP frame,strict priority transmission selection,parameter configurable CBS traffic shaping and gated scheduling.Board-level tests indicate that the system is fully capable of achieving the desired functionality.The focus of the thesis is on the circuit design of the frame scheduling module(Schedule module)in the TSN switch and the FPGA prototype implementation designed with Verilog.The Schedule module mainly performs the functions of CBS traffic shaping and gated scheduling.In the CBS algorithm,since the bandwidth reservation mechanism is established at the MAC layer,the actual bandwidth occupied by the physical service port after the shaping service cannot be accurately calculated,which is usually inconvenient to test.For the reason the CBS algorithm is improved in combination with the actual application requirements,and the relevant theoretical analysis of the bandwidth change before and after correction is given.In the gated scheduling scheme,in order to save bandwidth resources and strictly regulate the transmission window of the scheduled traffic,we extend the original entries of the GCL and design the length acquisition function of the next frame in the queue.Next,we discuss the further improvement of the GCL entries in a specific application scenario,which greatly saves the register resources of the system.Finally,for the problem that the gated scheduling scheme is difficult to test,a specified circuit inside the system for state monitoring is designed.Through the simulation and prototype system verification,all the above circuits can work as expected.