Design And Verification Of TTE End-system

In recent years,the country has vigorously developed the aerospace industry.From the Shenzhou spacecraft to the Tiangong space station,from Beidou navigation to Hongyan constellation,the traditional in-cabin communication technology has been unable to meet the current high-bandwidth,low-latency and high-reliability of aerospace electronic systems.Ethernet technology is the most common network communication standard protocol for existing LANs.However,the transmission of data packets in the standard Ethernet standard is “best effort” and cannot guarantee the real-time and reliability of key control data transmission,Ethernet is not suitable for direct application in aerospace and industrial control.Time-triggered Ethernet provides an effective solution for the transmission of mixed-critical services in aerospace and industrial control.The clock synchronization mechanism is the core technology of the network.The high-precision global synchronous clock established by this technology is a prerequisite for ensuring the strong real-time and reliability of time-triggered Ethernet data communication.Combined with the time trigger mechanism,TTE fully meets the requirements of the current aerospace and industrial control fields.Based on the research of TTE key technologies,this paper focuses on three parts: 1)design and implementation of real-time TTE End-system driver,2)design and implementation of TTE End-system FPGA logic function,and 3)multi-dimensional TTE end system verification.The main work of this paper: First,it summarizes the research background of TTE network and briefly introduces the basic concept of TTE network.Second,in-depth study of the key technologies and verification requirements of the TTE End-system,including data frame format,time synchronization technology,scheduling algorithm,error detection coding technology,specific design indicators and verification indicators.Third,the TTE End-system is designed and implemented,including CPU interface,TTE board driver,transmission processing module,receiving processing module,synchronization module,configuration module and TTE system working status.Fourthly,the TTE End-system is simulated and verified,and the problems encountered in the simulation and verification of the TTE End-system are analyzed,and the corresponding solutions are proposed.It is mainly divided into core module simulation verification,UVM-based simulation verification and board level verification.Fifth,the test results show that the TTE End-system fully meets the design and verification indicators,and puts forward the work that needs to be completed in the next step.It also puts forward new requirements for the verification of the TTE End-system.The innovations of TTE End-system in the design and implementation include: 1)Design and implement real-time TTE end system driver,and realize synchronization of FPGA board and host through interrupt.2)In the queue management module,the cache management method using dynamic and static combination not only utilizes the storage space effectively,but also ensures the storage of the TT service.3)The hierarchical address and address translation method of the TT service is proposed,which reduces the storage space used by the TTE end system in redundancy management by two orders of magnitude.