Research On MRR Fault Detection Method

In chip multiprocessors,the traditional electrical interconnect structures on chip can no longer meet the requirements of communication in terms of power consumption,bandwidth and delay.In the era of big data,there is an urgent need to develop a new technology to achieve efficient data transmission.In recent years,the use of optical links to replace metal interconnects has become a new solution due to the development of integrated photonics.Photonic Network-on-Chip(PNoC),as a trend and model for the development of the next-generation on-chip networks,can support higher bandwidth requirements as the number of chip cores continues to increase.The MicroRing Resonator(MRR),as a key optical component in PNoC,is particularly sensitive to temperature fluctuations and is highly susceptible to failure due to manufacturing defects,affecting the overall performance of the PNoC.How to effectively detect faults in MRR has become an urgent problem to be solved.PNoC mainly includes two parts: router and IP core.This paper focuses on the task of the Guangxi Natural Science Foundation Joint Funding Project(2018GXNSFAA138115).Taking MRR as the research object,different methods are used for fault detection of optical router and IP core composed of MRR respectively.The main research content of this topic include the following three parts:(1)The basic principle of MRR is studied,and its fault model is established according to the principle.The equivalent circuit is designed without fault and fault.Two fault detection methods are proposed based on the fault model: one is based on the graph in the fault detection diagram method,the optical router is first modeled as a pre-Fault-Check-Graph,and then the unweighted directed graph is obtained according to the pre-Fault-Check-Graph and the fault simulation.By determining the fixed point set elements of the router fault detection graph,gain the fault coverage rate;The other one is based on the fault detection method of the fault simulator.The optical router is modeled as a fault simulator structure composed of two-choice and multi-path selections,and the fault is simulated by the control signal to obtain the fault simulation result.The MRR's fault coverage rate can reach 100% under both detection methods.(2)The basic principles and general operations of Binary Decision Diagram(BDD)are studied,and the application of binary decision graphs in combinatorial logic circuits is studied.(3)A new basic logic gate and adder structure composed of MRR is proposed.The fault equivalent compression method and BDD are combined to detect the failure of the all-optical logic standard test circuit.Finally,the test vector of the fault and the test generation time are obtained.