Hardware And Software Co-design And Implementation Of Face Recognition System Based On Hardware Acceleration Algorithm

Face recognition is a research subject with wide application prospect in the field of bioinformatics.Most of the early research work is based on software to achieve related functions.With the increasing deployment of image acquisition systems in various application scenarios,image size and data volume increase rapidly.The face recognition process involves a large amount of calculation and classification.However,the processing of the computer is an instruction operation,and the calculation task in the recognition process can only be serially processed.This processing method requires a sufficiently large storage space,which increases the calculation cost.The low-cost,parallel computing and other features of FPGA(Field Programmable Gate Array)make it perform well in tasks with large computational complexity.Some functions in the processing process of the PC side are deployed in the FPGA,and part of the PC-side computing and storage pressures are shunted.This software and hardware co-design method solves the contradiction between the speed of improvement and the control cost encountered when the recognition function is completed on the software side.In order to realize the high-speed face recognition system based on FPGA and PC collaborative design,this paper first determines all the functional points to be completed,including real-time video image acquisition,image preprocessing without blocking,face extraction by feature extraction and classification.,through the Ethernet to transmit image data by FPGA to PC and the function of result display after identify.The linear programming algorithm is used in the design to divide the function points into hardware and software.The FPGA side performs real-time image acquisition,grayscale conversion,filtering and other pre-processing functions,and implements face detection algorithm based on Haar feature cascade classifier using highly pipelined micro-architecture.The rich parallel arithmetic unit in FPGA makes this design have high detection accuracy and low latency for face detection performance.In addition,based on the PHY chip mounted on the development board,this paper realizes the high-speed transmission function of Gigabit per second between FPGA and PC through Ethernet,which is used to transmit the image data superimposed with the face detection result window to the computer.The algorithms deployed in implementing face recognition have many options,among which SVM(Support Vector Machine)and NN(Neural Network)achieve the best performance under the criteria of detection rate and false positive rate.SVM is the most widely used algorithm for machine learning due to better generalization performance.In this design,after receiving the image data under the UDP protocol from the FPGA side,SVM algorithm is adopted to realize the face recognition function of Haar cascade classifier's face detection result window.Compared with the equivalent software implementation,the recognition accuracy is located in a similar interval slightly larger than the software implementation accuracy,and the system's recognition speed is 1.5 times higher under the real-time video input of 640*480 resolution.