Algorithm Of Intelligent Face Recognition And Implementation Of FPGA

Face automated recognition technology is the hot topic of pattern recognition and image processing. With the development of lives, people are eager to get the fast identity recognition technology. As the one of the most important biology recognition technology, the face recognition becomes more and more valued.This paper introduces the mechanism, history, formula, disadvantage and advantage of face recognition including face detection, eye location, preprocessing, PCA and ICA algorithm. It also introduces the project, the partition of system and the platform of hardware and software. According to the FPGA design code style, we use the Verilog HDL to translate the algorithm on ISE platform, and optimize C++ algorithm. We compare the verilog data result and C++ data result through simulation and evaluate them. The code are synthesised and implemented on VirtexII pro board. The main work is as follows:First, I study the Xilinx VirtexII Pro FPGA hardware platform and operated the RS232, JTAG, sdram. I design, compare and simulate the two algorithm of Coreconnect opb bus arbiter. I study the ISE and VC++ software platform, so I can debug the verilog and C++ code synchronously. After this study, I can get the maximum use of hardware resource and best choice of device. Also, it can fasten design and debug flow of project.Second, I compare the face detection, eye location, preprocessing and recognition of face recognition algorithm and choose the best algorithm of each kind. I use Adaboost as the face detection algorithm because it's whole behavior. I use small block combination as the eye location algorithm because it is fast and exact. I use the histogram equilibrium as the preprocessing algorithm because it is easy and effective. The choice of PCA and ICA is because it can weaken the effect of appearance and light.Last, according to the FPGA style and effect of C++ algorithm, I optimize the algorithm in verilog HDL hardware language. The video input and output module is the precondition of algorithm processing, it provides the algorithm with the input data. Preprocessing optimizes the C++ code, develops the speed and reduces the quantity of calculation. The 16 bits calculator gives more choice between the FPGA IP core and my design to develop the speed of design. I simulate and debug the verilog and C++ design synchronously, so I can compare the result at any moment. All of the design module pass the simulation and get good result, synthesized and implemented on FPGA.