Study On FPGA Implementation Of Signal Processing For Continuous Wave Phased Array Radar

The LFM signal has a certain time-width and bandwidth,so it has been extensively studied in the measurement of target distance and speed.The continuous wave signal can provide strong transmit power and the distance blur is small,so it is widely used in the detection of long-distance targets.Therefore,the LFMCW signal is often used as a carrier signal,and can be used to measure the speed and distance of the long-distance target.Using the similar measurement method of detecting target speed,distance and angle in the pulse system,this subject completed the digital up-conversion and beamforming in the transmitting,and the digital down-conversion and all process of signal processing in the receiving.Finally,the measurement of speed,distance and angle of multiple targets in the airspace is achieved,and the effect of active warning is attained.This paper mainly discusses the related processing methods of receiving and transmitting in signal processing.Including Digital Up-Conversion(DUC),interpolation filtering,transmitting beamforming,Digital Down-Conversion(DDC),decimation filtering,transmitting interference directly suppressed,matched filtering,and angle measurement in Sum Difference Beams,Moving Target Detection(MTD),Collaborative Forecast And Replenishment(CFAR).This paper uses ISE,MODELSIM and other simulation verification tools to achieve the simulation of related algorithms and FPGA implementation and related debugging.This article is divided into four parts.1.The main algorithms used in the design of the transmitting and receiving are introduced.Including DUC,interpolation filtering,transmitting beamforming,DDC,decimation filtering,transmitting interference directly suppressed,and angle measurement in Sum Difference Beams,matched filtering,MTD,CFAR.At the same time,according to the design requirements,the structure of some algorithms is improved to ensure the reliability of processing.2.This design completes the design of the overall architecture of the transmitting and receiving and the division of the corresponding modules.Then the relevant algorithm is verified by algorithm simulation tool.3.This design completes the FPGA implementation of each module,then combine with ISE and MODELSIM and algorithm simulation tool to verify the function of each module.This design optimizes the hardware implementation structure and ensures the rational use of resources.4.This design completes the online debugging,desktop debugging,darkroom debugging and final field debugging of each module,and analyzes the final performance with Chipscope and algorithm simulation tool.Finally to ensure this design meets the expected requirements.