Design Of 10-bit Low Power Successive Approximation Register Analog-to-digital Converter

Nowadays,more and more emerging applications,such as wireless sensor networks,implantable biomedical devices,portable detectors,etc.,are rapidly developing.the analog-todigital converter is used as an analog signal to digital signal transfer station in these application,which needs to have a low power consumption and small area.This paper designs a 10-bit fully differential successive approximation analog-to-digital converter(Full differential SAR ADC).The main part is composed of a main part such as a digital-to-analog converter(DAC),a comparator,a sample-and-hold switch,and digital control logic.The DAC and digital control logic,using the new "Double Capacitor Switching scheme(DCS)",saves 75% of the DAC area and 99.3% of the DAC power consumption compared to traditional switching strategies.And use the 6MSB+ 3LSB structure to balance the area and linearity.The comparator uses an NMOS wide swing comparator to ensure that the change in the common-mode voltage of the DAC output does not affect the final result under this switching strategy.The whole circuit adopts HHNEC CZ6H+ 1P4 M 0.35?m process design,the working voltage is 5V,the whole circuit simulation is carried out under the sampling rate of 100KS/s and 0.49 KHz input signal.The measured signal-to-noise ratio of the analog-to-digital converter is 60.1dB,no The spurious dynamic range is 71.5dB,the signal-to-noise distortion ratio is 59.8dB,the total harmonic distortion is 71.0dB,the effective number of bits ENOB is 9.64 bits,the average operating current of the ADC is 58.36?A,and the average power consumption is 291.8?W.Its FOM is 3.65pJ/con.