Research And Verification Of Variable Delay Of CCFD Self-interference Rejection

In the co-time co-frequency full duplex communication system,the transmit signal of equipment itself causes strong interference to the detection of useful received signal.Therefore,it is necessary to sufficiently suppress the self-interference signal in the device.The self-interference signal time-delay is an important parameter that affects the self-interference rejection performance.Integer-time sampling rate delayers can only roughly correct time-delay,and cannot meet the performance requirements of full-duplex systems.In order to achieve more accurate time-delay correction,variable delay is introduced into the full-duplex system to further improve the delay correction accuracy,thereby improving self-interference rejection performance of the system.The thesis designs and analyzes the variable delay in the full-duplex system.The main contents include:First,re-designing the variable delay of the farrow in the digital domain,by minimizing the residual self-interference signal power criterion.In order to correct time-delay accurately,this thesis gives a closed expression for solving the filter coefficients,and carries out simulation and analysis finally.Simulation results show that when the self-interference signal's bandwidth is 0.5 MHz and 10 MHz,the self-interference rejection capability is improved about 6.5 dB and 3.7 dB higher with the designed variable delay device,compared with the fractional farrow filter under LS(Least-Squares)standard.It enhances self-interference rejection performance.Secondly,this thesis designs the overall architecture of self-interference rejection.The time-delay synchronization module is divided into two sub-modules,and the implementation principle and processing flow of each module are introduced detailedly.Finally,the design scheme is simulated.Simulation results show that under the condition of interference-to-noise ratio of 60 dB,the self-interference rejection ratio is in the range of 27.97dB~48.97 dB when fractional delay correction is completed.And the fractional delay value is smaller,the self-interference rejection ratio is larger.Moreover,the self-interference rejection is related to the normalized bandwidth,and the smaller the bandwidth,the larger the self-interference rejection.Thirdly,by testing on the hardware platform,this thesis verifies the feasibility of the variable delay scheme designed from two perspectives of function and performance.The test results show that the self-interference signal can be reconstructed and cancelled after the fractional variable delay filter.And the smaller the normalized bandwidth,the better the cancellation ability,that is,the higher the self-interference rejection ratio.Under the condition that the interference-to-noise ratio is 60 dB,the self-interference rejection is about 28.79 dB.This is basically consistent with the simulation results,which proves the feasibility of the design scheme.The thesis studies the variable delay technology based on the residual power minimization criterion,and implements and verifies it on the hardware platform.It provides a theoretical reference for further improving self-interference suppression.