Research On Design Of Energy Efficiency VLSI Circuit Based On Statistical Error Compensation

With the rise of the Internet of Things and portable devices,energy consumption has become a growing concern for IC design engineers,and more and more technologies are used to reduce the power consumption of the chip.Because the energy consumption of digital circuits is mainly dynamic energy consumption,and the dynamic energy consumption is proportional to the square of the power supply voltage,in these technologies that reduce power consumption,the technology that can reduce the power supply voltage is often the most effective.However,as the power supply voltage decreases,the critical path delay of the digital circuit increases,and the operating frequency of the circuit is correspondingly reduced,which does not satisfy the requirements of the computing power of the portable device.Therefore,how to reduce the energy consumption of the chip on the basis of ensuring the computing power of the chip has become a matter of great concern.We studies a class of digital signal processing applications in portable devices that can effectively reduce the energy consumption of chips,namely statistical error compensation(SEC).Because this kind of technology compensates the soft error of the operation circuit under low voltage by means of error detection and correction,it can reduce the minimum working voltage of the circuit while keeping the working frequency constant,thus the throughput capacity of the datapath is kept,at the same time the circuit's energy efficiency is improved.We first introduces the development of statistical error compensation technology and its technical characteristics,and then explains and analyzes several typical implementation forms.This paper focuses on the embedded algorithm noise-tolerance technology,which is one of the most important form of statistical error compensation technology,and explains the main principle and implementation of the technology in detail.On this basis,this paper studies the implementation of embedded algorithm noisetolerance technology on an 8×8 multiplier,and reduces the hardware overhead of its error detection and correction module by the “judge threshold scaling” method proposed in this paper.Compared with other multipliers based on this technology,the design of this paper can reduce energy consumption by 16%.Then,this paper studies the specific implementation of FIR digital filter based on statistical error compensation technology.By studying its circuit characteristics,this paper proposes several targeted optimization methods,including the embedded implementation method of constant coefficient multiplier and the optimization method of critical path.Finally,the transistor-level simulation of the FIR digital filter based on the above method is carried out.The simulation results show that the minimum operating voltage of the FIR digital filter based on statistical error compensation technology is 1.24 V when the operating frequency is 198 MHz,which is 0.42 V lower than other structures,and its energy consumption is reduced by 26.82%.