The Hardware Platform Design For Frequency Diverse Array Radar Simulator

With the development of the theory of Cognitive Electronic Warfare(CEW)and Frequency Diverse Array(FDA)radar,the research achievement need to do some engineering verification and implementation.On the market,many companies designed some hardware platforms base on Software Defined Radio(SDR),but there are some shortcomings,such as high price and some resources do not opening to users.The manufacturers of chip also issued some boards,that are designed for chip development and promotion,there are big limitations in processing power,practicality and flexibility.Therefore,it is necessary to develop a hardware platform to meet the actual demand and realize the transformation from theory to application.Through investigation and research of the hardware platform in the market,combined with the specific requirement,this article starts with the design objectives and the problems to be solved,complete the development of hardware platform.The platform adopts the idea of modular,divides the design into rf and dsp which interconnected by FMC(FPGA Mezzanine Card)connectors.The part of rf complete the pretreatment of the rf signal,ADC,DAC,the part of dsp complete the processing of digital signal and data transmission,under certain conditions,for different systems,it only needs to replace modules or reprogrammed the system,the idea of modular can improve reconfigurability and flexibility of the hardware platform.The part of dsp adopts the framework of DSP and FPGA,the framework gives full play to the parallel processing capabilities of FPGA and complex algorithm implementation capabilities of DSP,Clear division of labor and complement each other,have better performance and flexibility.Based on the architecture of 6U VPX,the platform has the capability of high-speed data exchange and can be used as a sub-module in large communication systems.Meanwhile,the single board can also be used as an independent communication system or hardware debugging platform to meet the current hardware requirements.This thesis completes the design and debugging of the hardware platform,and expounds the design ideas of each sub-module and the overall scheme.Through analysis of the main parameters for selection,read a large number of chip manual,interface protocol and reference design,complete the system design and schematic diagram.After the completion of PCB and welding,hardware debugging shall be carried out according to the established steps to eliminate problems,and finally all chips shall be in normal working state to complete the debugging of hardware circuits.This thesis also studies the interface of DDR3(Double Data Rate 3),realizes the function of high-speed Data storage though FPGA,complete debugging of SRIO(Serial RapidIO)switching chip and realize the exchange of high-speed data between multiple FPGA GTX transceivers.Finally,this thesis analyzes and studies the agile transceiver chip of AD9361,use FPGA to configurat the register,combine the rf module and the hardware platform,complete the transmission and reception of rf signal and realize closed-loop test.