Design And Implementation Of Heterogeneous Multi-core System For Wireless Receiver Of Large-scale Neuron Activity Signals

With the continuous development of emerging technologies in the information science,various applications have increasing demands on “computing power”.Heterogeneous multi-core systems can take full advantage of general-purpose processors and dedicated processors,and it can make system more flexible and highperformance.However,such systems exist two major difficulties in system design:task partition and communication between processor cores.At the same time,a new neuron activity recording system is needed to assist the research of brain information coding principle,which requires low power,high-speed and wireless in big-data transmission.In this paper,we study that two difficulties,and implement the wireless receiver of large-scale neuron activity signals by the proposed design method,which is based on heterogeneous multi-core system.The research contents include:Firstly,we study the design flow of heterogeneous multi-core system,and analyze the system constraints of CPU+FPGA architecture.Then,a new design method for heterogeneous multi-core system is proposed,and it takes executing time,hardware area,power consumption and system cost as the system constraints.After the attribute of each constraint is obtained,the system task can be partitioned based on AHP and multi-objective optimization.In addition,this paper studys the data interaction between CPU and FPGA,and proposes two communication methods: based on AXI-GP and AXI-HP interface.Secondly,this paper determines the overall scheme on the system requirement of large-scale neuron activity signals wireless transmission.For the scheme of channel coding and decoding,the algorithm and hardware circuit are designed,and the frame format of wireless transmission is finally determined.Finally,the wireless receiver of large-scale neuron activity signals is implemented by the proposed design method of heterogeneous multi-core system.After testing,compared with the original pure software implementation,the method was accelerated by 18.73 times.In addition,the Viterbi decoding algorithm is improved.The improved LUT usage rate is reduced by 38.63%,which makes the system meet the constraints of FPGA design on hardware resource usage.