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Design Of Low Power And Highly Linearty Tunable Complex Filter

Posted on:2019-05-02Degree:MasterType:Thesis
Country:ChinaCandidate:Y J YouFull Text:PDF
GTID:2428330596460784Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the fast development of communication technology and semiconductor technology,integrated circuit progresses to the direction of low power and portability.For decreasing the power of the system,low voltage technology is more and more popular among the designers.However,the decrease of the power doesn't make the threshold voltage of the MOSFET scale down since the extreme low power will bring the risk of current leakage.Therefore,how to design the analog circuit with the condition of low power has become a hot spot and difficulty.The thesis first summarizes the background and research status of the filter,and analyzes several RF receiver architectures.Since low-IF receiver architectures handle signals in the lower frequency,power consumption is low,dc offset and 1/f noise have little effect on it,low-IF receiver architectures are used to implement the Global Positioning System(GPS).Secondly,several methods for low-power design are analyzed and the design mode with low supply voltage is finally adopted.The system block diagram is obtained by deriving the function of the complex filter,and the system block diagram is converted into the second-order complex filter unit in combination with the transfer function of the second-order low-pass filter.In order to further reduce system power consumption,a low-voltage transconductance amplifier circuit and a manual calibration method are designed.The transconductance amplifier structure stacks two transistors between the power supply and ground,eliminating the need for a tail current source design.Sufficient voltage margin is provided for the input and load tubes,and a common-mode feedback circuit is used to stabilize the output common-mode level,thereby significantly reducing the power consumption of the filter.This thesis is based on the SMIC 40 nm process layout design.The test results show that when the input reference current is 10 uA and the power supply voltage is 0.7V,the center frequency of the complex filter is 2MHz,the bandwidth is 1.9MHz,the passband gain is 10.1dB,the image rejection ratio is greater than 20 dB,and the input third-order interaction The adjustment point IIP3 reaches 8dBm,the power consumption is 0.43 mW,and the test function basically meets the requirements of the indicator.
Keywords/Search Tags:low voltage low power, Low-IF structure, complex filter, operational transconductance amplifier
PDF Full Text Request
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