Research And Hardware Implementation Of Key Module For RD Imaging Algorithm

Synthetic Aperture Radar(SAR)is an active microwave remote sensing imaging radar,which can obtain high resolution two-dimensional SAR images.The SAR can obtain the radar image by transmitting electromagnetic wave and receiving the echo.Compared with the infrared,optical and other traditional imaging methods,it has many advantages,such as all-day,all-weather,penetrating and high resolution.So SAR has high practical value in military and civil applications.In addition,with the development of SAR system in multi polarization and real-time,echo data is more and the processing time is shorter.So the traditional digital signal processor can't meet the requirements of real-time imaging system.So the imaging algorithm of SAR is deeply studied in this paper.Firstly,I introduce the basic principle of SAR imaging system,and explain the reason why SAR can get high resolution in both range and azimuth.Then linear frequency modulation signal and its characteristics,the process of matched filtering and pulse compression are analyzed.Secondly,the ground target is scanned by SAR in the side looking strip mode is modeled by using Matlab.The echo model is analyzed in time domain and the SAR echo data are generated.Then,the Range Doppler(RD)imaging algorithm is modeled,and the SAR echo data is processed by RD system.The imaging results show that the SAR imaging system model has good imaging effect in the positive side view.In addition,the key module of RD imaging algorithm--pulse compression module is designed and implemented.Firstly,the hardware architecture of pulse compression in frequency domain is designed and it is clear that Fast Fourier Transform(FFT)and complex multiplier are the key units to realize pulse compression;Then,the hardware circuit architecture of FFT is designed based on the FFT algorithm of frequency domain decimation radix-2~2 and single delay feedback structure;Then the circuit structure of traditional butterfly arithmetic unit is improved,and the new circuit structure's resource usage is reduced half.Booth complex multiplier replaces the traditional complex multiplier and the number of partial product reduced to half,so the consumption of hardware resources greatly reduces and critical path was shorten.In addition,three new types of constant complex multipliers are designed,consist of“CSD”,“coefficient enlarging”and“coefficient enlarging and selection”complex multiplier.Compared with the traditional rotating factor multiplier,the new complex multiplier greatly reduces the hardware resource consumption and improves the system performance.Finally,FFT unit and pulse compression module is described by Verilog HDL and is simulation in function by ISE.Then the module functional is verified by Matlab and the results show that the function of FFT unit and pulse compression module are correct.compared with the traditional FFT and pulse compression structure,the improved structures save hardware resources about 2/5.