Study On Ultra-Low Voltage Noise Immunity Circuir Design

With the development of wearable devices and embedded medical devices,the application of ultra-low power circuit designing increases significantly.In order to keep the power dissipation at a relative low degree,lowering the supply voltage is one of the most efficient way to save power consumption.But lowering supply voltage brings us the lower noise margin and future electronic devices are expected to work in even worse noisy environment.So the study based on the ultra-low voltage noise immunity circuit design is a promising and valuable research direction.In this paper,we proposed two new noise immunity circuit structures based on the previous structures.The first structure named INVL by having a deep insight in the sequential logic feedback circuit structure.The second structure named INS on the understanding of physical characteristics of MOSFET and regeneration of CMOS technology.We use these structures to design the gate circuits as basic logic cell library.And we simulate and test some parameters of these circuits such as frequency,power,noise immunity and so on.The simulation results show that compared with SIM_MRF^[23],INVL and INS improves 22%and 70%energy consumption respectively with the same noise immunity as SIM_MRF.As the different function modules show the different performance parameters,we propose a new hybrid circuit design method based on MAS_MRF and INS.We design an 8-bit carry-lookahead adder?CLA?as a sample circuit by using four kinds of basic units.And four chips are fabricated and tested to compare the difference performance.Measurement results show that compared with previous works,the HYD_CLA improves14%noise immunity and reduces 11%circuit area than the SIM_CLA,saves 53%E/cycle than MAS_CLA,which confirms that the new hybrid circuit design method is effective.