Research On Group Delay Optimization Technology Of IIR Digital Filter

As an important part of digital signal processing,digital filters have attracted much attention and have been widely used in communication,image processing,and audio processing.Common digital filters are mainly divided into Finite Impulse Response(FIR)filters and Infinite Impulse Response(IIR)filters.Compared to FIR digital filters,IIR filters have lower group delay,higher computational efficiency and better frequency selectivity.However,the phase of the IIR digital filter is non-linear and the non-linear phase results in a non-constant group delay.The signal components of different frequencies generate different delays through the IIR filter,which causes distortion.Therefore,group delay optimization has become a key issue in the design of IIR digital filters.This paper focuses on the group delay problem of cascaded IIR digital filters,and proposes a population delay optimization technique,which is studied from the following aspects:1.In terms of structural technology,in order to reduce the output signal distortion of the filter caused by non-constant group delay,this paper proposes a group delay compensation optimization method suitable for cascaded IIR digital filters.The variation of the group delay in the passband range is reduced by connecting an all-pass equalizer to the output of each stage of the cascaded IIR digital filter.The stability of the inserted all-pass equalizer and the entire filter system is evaluated by means of pole-zero analysis.2.In the hardware description and function verification,this paper uses Verilog HDL hardware description language to design the cascaded IIR digital filter proposed in this paper.The module simulation and system simulation were carried out on the Modelsim simulation platform,and the input and output of the filter were analyzed by Matlab.In addition,the EDA tool DC(Design Compiler)is used to logically synthesize the IIR filter,and the IIR filter in parallel and serial data transmission mode is verified by FPGA.3.In the aspect of chip design implementation,based on the group delay optimization method proposed in this paper,a 10-bit IIR digital filter is designed and implemented.Based on the 0.18?m CMOS digital standard cell library,Synopsys'ICC(IC Compiler)was used to complete the digital circuit design flow such as automatic place and route and clock tree synthesis.Finally,the chip package and test scheme are given,and the chip test is completed.For the group delay optimization method proposed in this paper,when the 1st and 2nd order equalizers are used for circuit optimization,the variation of group delay is reduced by 28.19%and 49.93%respectively in the passband range of 0~100Hz.Compared with the existing results,the proposed group delay optimization method is small and easy to implement.The IIR digital filter designed in this paper is implemented in 0.18?m CMOS process.The test results of the chip show that the maximum operating frequency of the filter is 18MHz,the area and power consumption are 0.102mm~2 and 0.8490mW,respectively,with smaller chip area and lower.The circuit power consumption is easier to implement in actual chip,which proves that the proposed group delay optimization technology meets the development trend of low power consumption and miniaturization of ECG acquisition system.