Research And Implementation Of Downlink Channel Estimation For LTE-A Air Interface Monitoring Analyzer

LTE-A is the mainstream of current mobile communication technologies,which provides users with a rich multimedia service experience.However,with the explosive growth of data volume,network problems become complex.Through using the air interface analyzer to monitor the LTE-A network in real time,operators can locate faults accurately,collect the data of users and optimize the network so as to enhance the experience of users.Therefore,the development and research of LTE-A air interface monitoring analyzer is particularly important.The thesis is based on the national science and technology major project “New Generation Broadband Wireless Mobile Communication Network”.Combined with the LTE-A system protocol standard and the existing channel estimation algorithm,the downlink channel estimation scheme that meets the project requirements is designed,implemented and tested.The main work is as follows:1.The physical layer of LTE-A system is studied,and the overall architecture of the LTE-A air interface monitoring analyzer and the downlink baseband processing flow are designed on the basis of the demand analysis of the LTE-A air interface monitoring analyzer.2.The research and scheme design of the downlink channel estimation algorithm for LTE-A system is carried out.Firstly,the LTE-A downlink channel estimation process is designed.Then,considering performance and complexity of the system,the implementation algorithm of downlink channel estimation module used in the LTE-A air interface monitoring analyzer is determined,that is,the LS algorithm is used at the reference signal position,and the LMMSE sliding interpolation algorithm based on SNR estimation in frequency domain and linear interpolation algorithm in time domain are used at the data position.3.Based on the proposed scheme,the FPGA design of the downlink channel estimation module is performed.The top-level modules and the sub-function modules of the downlink channel estimation are designed according to the top-down and modular ideas.The frequency domain interpolation module uses 12 pipeline to increase the operation rate,and the time domain interpolation module performs parallel pipeline processing with the frequency domain interpolation module to reduce the delay.The FPGA implementation is completed by using the verilog hardware description language for the downlink channel estimation module in Xilinx's XC7Z100-2FFG900 I chip.4.The downlink channel estimation module is tested.Firstly,ModelSim is used to verify the correctness of the channel estimation scheme.Then,the performance of the channel estimation scheme is tested from the dimension of resource occupancy and time consumption.Finally,the channel estimation module is applied to the LTE-A air interface monitoring analyzer for integration test.The results show that under the circumstance of maximum bandwidth of 20 MHz,the channel estimation scheme proposed in this thesis takes a total time of 0.708 ms to complete a sub-frame channel estimation,which can meet the requirements of real-time performance of the system.Moreover,the occupancy rate of each chip resource of the proposed scheme is less than 10%,which meets the application requirements.