Design And Realization Of Frequency Synthesizer For A Broadband High-Resolution Photonic Analog-to-Digital Convertor

With the rapid development of radar,modern communication and electronic reconnaissance,the requirements for analog-to-digital converter(ADC)on bandwidth,sampling rate,and precision are becoming higher and higher,which make it difficult for electronic ADCs to fulfill these requirements due to the electronic.The photonic analog-to-digital convertor(PADC)is developed by utilizing the advantages of microwave photonic technology,such as low time jitter and broad bandwidth.Nevertheless,the sampling rate and resolution of PADC system are still limited by the inconsistence in electronic quantization and digital data processing.A PADC system based on parallel demultiplexing is introduced in this thesis to overcome this limitation,and a frequency synthesizer to drive this PADC is designed and implemented.The main research work is described as follows:1.The architecture of a frequency synthesizer for multichannel PADC is introduced.The synthesizer produces the required RF signal to drive the parallel demultiplexing module in the PADC system,thus realizes parallel demultiplexing for the input signal.The configuration of frequency synthesizer is optimized to satisfy the demand of PADC system with the advantages of high efficiency,convenience of testing,and brief layout.2.According to the configuration and specifications of the frequency synthesizer the rules for the selection of devices and related parameters are presented.The selected devices are tested and the results are evaluated.Then,the frequency synthesizer is configured out by the tested devices and its comprehensive performance is tested.The experimental results show that the harmonic suppression ratio is 55 d B and the SNR reaches 60 d B.The frequency synthesizer is installed into the PADC system and its influence to the effective number of bits(ENOB)of a single channel in the PADC is studied.The ENOB of the PADC system are measured to reach 7.73 bits at 9.812 GHz input carrier and 6.9 bits at 35.412 GHz input carrier,respectively.The results verify the effectiveness of the frequency designed.