Image Connected Component Parallel Labeling And Eigenvalue Statistics IP Design And Verification

The feature extraction of Image target is an important part of target recognition.Connected Component Labeling(CCL)is a necessary step for target feature extraction.It has a wide range of application requirements and scenarios,and is mainly applied to image processing systems such as automatic target recognition and tracking.The system usually needs to iteratively segment the image and call the CCL module multiple times,which puts high requirements on the processing speed of the CCL module.The speed of using software to achieve image CCL is slow,it is difficult to meet the real-time requirements of embedded image processing systems.The hardware is generally used to accelerate module,taking advantage of hardware parallelism,thereby achieving higher processing efficiency than software.In this paper,FPGA-based image Connected Component Parallel Labeling and Eigenvalue Statistics IP are proposed and designed.IP collects connected component's eigenvalue while connected component labeling.It does not need to cache intermediate result images,and finally outputs the connected component's eigenvalue,reducing resource overhead and processing time.IP processes 8 pixels per clock cycle and has a high data throughput rate,which can be applied to the field of embedded image processing with high real-time requirements and limited hardware resources.Aiming at the problem of large critical path delay of IP initial labeling circuit,it is proposed to realize parallel labeling by modular circuit and the architecture of advanced calculating new temporary label value,avoiding the adder cascade of initial labeling circuit,reducing critical path delay and improving operating frequency of the circuit.Aiming at the problem that the input data format of the IP and the initial labeling circuit are not matching,the data splicing algorithm and the unified state automata are used to realize the data splicing,and the input data format mismatch problem is solved by using fewer resources,so that the IP can process any arbitrarily size image.Aiming at the problem that the processing speed of the IP initial labeling circuit and the eigenvalue statistical circuit are not matching,a data transmission scheme combining bypass and control FIFO reading and writing is proposed to realize the data transmission between the initial labeling circuit and the eigenvalue statistical circuit.There will be no data congestion in the whole circuit,increasing data throughput.According to the above scheme,this paper completed the work of IP circuit design,function verification,synthesis,place and route.At present,IP has been embedded in the image processing system and implemented on the Xilinx K7325 t board.The IP working clock reaches 130 Mz,the data throughput rate is 934.70 M pixels/s,and it takes 0.35 ms to process a frame picture of 512 ? 640 size,with less resources to meet the real-time requirements of embedded image processing systems.