An Improved ASIC Implementation Of Multi-value Connected Component Labeling

Connected component labeling is a common image analysis operation. However, because there are a lot of comparison and re-labeling operations, it often become the bottleneck of real-time image analysis system.In response to this problem, the connected component labeling algorithm and its ASIC implementation are studied.Architecture design, logic design, synthesis, timing analysis and verification of the chip has finished.And now back-end design of the chip is in process.Major studies in this dissertation are:1. Basing on the work of the LABEL chip, the architecture of the CCL chip is proposed to meet function and demand of the chip.The architecture compromises in both performance and cost.Settings of on-chip image memory, pixel buffer and label buffer, FIFO, character memory are studied. The architecture makes only a small increase in chip area, however it shortens processing time of the original 1/4. Besides, it eliminates an asynchronous memory for data exchange between CCL chip and main processor, which can reduce the complexity of the application system.2. Logic design of the chip is accomplished. Reset logic design, input-output interface design and controller design is the focus of this dissertation.3. Synthesis and timing analysis of the chip are finished.4. Dynamic functional verification, formal verification and verification with FPGA are all carried out.Synthesis results shows that the clock frequency of the chip can reach 150 MHz and the clock frequency of the external processor can reach 110MHz.The equivalent area of the chip is 430K logic gates.The chip can label an 320*256 image within 1.8ms when the clock frequency of both the external processor and the ASIC is 100MHz,which includes time to load original image and read out results.