Research For N-path Filter Applicated In Analog Radio Frequency Front-end

Due to the prevalence of personal wireless terminal devices,more and more multi-mode RF-systems based on wireless-communication protocols have been integrated in one device,RF-systems are required to improve integration level,reduce power consumption and area,and increase reliability.The traditional way is to add a SAW-filter in front of the RF-receiver to solve the interference from multi-standard and multi-mode in RF-system,at the expense of increasing cost and volume of the handheld devices.In order to replace those bulky and expensive SAW-filters,periodic time-varying mechanism can be used to realize impedance frequency transformation,translating low center-frequency,low Q on-chip capacitor filter into high center-frequency,high Q,tunable N-path filter.However,N-path filter has lots of non-ideal effects limiting its application.In this thesis,several key issues such as insufficient harmonic rejection,harmonic folding and center-frequency offset that affecting N-path filter's performance have been analyzed through theoretical derivation and simulation.To solve these key issues,complex impedance and active Gm-C structure have been introduced to eliminate the harmonic and correct the center-frequency offset respectively.The performance of the Gm-C Enhanced N-path filter has been verified through simulation,and an active Gm-C complex impedance has been proposed to eliminate harmonic and correct center-frequency offset simultaneously.Because the impedance frequency transformation of the N-path filter is realized through N phases non-overlap clock driving those switches,the overlap and rising/falling time of the clock have direct influence on N-path filter's gain.There are mainly two ways of generating N phases non-overlap clock,which are CML logic flip-flop frequency dividing and CMOS logic D flip-flop frequency dividing,this thesis simulated these two kinds of clock generation circuits for N-path filter,and compared their pros and cons.