Design Of RFID Back-end Circuit Based On Amorphous Oxide TFT

Amorphous oxide TFTs represented by a-IGZO thin film transistors(TFTs)have high mobility,high switching ratio,high transmittance and other advantages,and their applications in the field of radio frequency identification(RFID)technology have gradually attracted people's attention.The performance of the RFID tag reading circuit is important for increasing the tag sensing distance,improving the information storage capacity and communication stability.Since the performance of p-type transistors remains inconsistent with that of n-type transistors,TFT-based RFID tag back-end circuits are generally implemented by unipolar transistors.Compared with chips using silicon-based processes,it still needs to be improved in terms of power consumption and swing performance.Therefore,this paper optimizes the RFID tag back-end reading circuit from two aspects: logic gate circuit design and system circuit architecture.By studying the topology of existing inverters,a three-stage inverter with dynamic load is proposed.The inverter replaces the diode-load in Pseudo-CMOS inverter with dynamic load driving by output voltage.With this design,the driving signals of input TFT and load TFT in each branches are complementary,which realizes zero quiescent current in inverter and reduces the power consumption.Since the driving voltage of the pull-up tube forms a positive feedback with the output voltage,the inverter clamps the output voltage amplitude through the feedback path to increase the output voltage swing.Aiming at the problem that the D flip-flop consisted of NOR gates which based on pseudo CMOS has high power consumption,a D flip-flop which consist of external-bias NOR gates is proposed and the circuit topology is optimized.When the clock signal is high,the external bias voltage clamps the sustain-block circuit output low voltage to reduce the input stage current and latch the output signal.The analysis shows that the proposed low-power D flip-flop effectively reduces the static power consumption while maintains the response speed.A pre-set clock oscillator is proposed.The inverter's load transistor is driven by the input voltage of the previous inverter whose phase is opposited to the input voltage.This design can achieve high oscillation frequencies while reduce power consumption and increase output swing.Because of the problem that the existing three-phase clock Manchester code circuit has a single function and requires multiple clock signals,a dual-mode Manchester coding circuit is designed,which can realize standard Manchester coding and differential Manchester coding driven by only a single clock signal.The simulation results show that,compared with the pseudo CMOS inverter,the output swing of the three-stage inverter with dynamic load is increased by 13.13%,and the quiescent current is reduced by 98.54%.Compared with the traditional D flip-flops,the D flip-flop proposed in this paper can reduce the power consumption by 78.07% while maintaining the output swing and response speed.