Study On Device Physics Of Amorphous Indium-gallium-zinc Oxide Thin Film Transistors

Recently, amorphous indium-gallium-zinc oxide thin film transistors (a-IGZO TFTs) and other amorphous oxide semiconductor based TFTs have been attracting worldwide attention. Comparing to their conventional silicon based counterparts, the a-IGZO TFTs are highlighted by their excellent features such as high mobility, low leakage current, good uniformity and low fabrication cost, which makes them a promising candidate for the application of new-generation displays. However, due to the amorphous nature of a-IGZO, the a-IGZO TFTs are still suffering from a series of technical problems, which restrict their further applications. Some of the major issues include high contact resistance in scaled down devices and poor long-term reliability under bias and illumination stress. To solve these problems, in-depth understanding of the related device physics is indispensable. In this thesis, we systematically utilize several characterization methods to investigate the contact and interface properties of the TFTs. Our aim is to reveal the physical factors that dominate the contact and interface properties of the a-IGZO TFTs. The major results of this thesis are listed below:1. Staggered bottom-gate a-IGZO TFT samples are fabricated by dc sputtering with a series of post-annealing temperatures for further comparative study of device physics. Decent electrical performance is achieved by optimizing process parameters. In order to draw solid conclusions in device physics studies on contact properties and interface properties, accurate extraction of electrical parameters such as threshold voltage and effective mobility of the TFTs is necessary. For this purpose, the applicability of conventional parameter extraction methods to a-IGZO TFTs is discussed. Accordingly, an extraction method which could properly deal with the nonlinear relationship between mobility and gate voltage in a-IGZO TFTs is proposed. By fitting the transfer characteristics of the devices with this method, the threshold voltage and effective mobility of a-IGZO TFTs annealed at different temperatures are extracted. The underlying physics of the relationship between these parameters and annealing temperature is discussed.2. In order to study the source/drain contact properties of a-IGZO TFTs, the contact resistance should be accurately extracted in the first place. For this purpose, the channel resistance method is optimized for a-IGZO TFTs considering the variation of contact resistance with gate voltage. Then the contact resistance and transfer length of a TFT operating in linear region under different gate biases are extracted. Both the contact resistance and transfer length are found to decrease with increasing gate voltage. As the contact resistance follows the trend of channel resistance variation with increasing gate voltage, the bulk a-IGZO underneath the contact electrodes is considered to be a part of the total contact resistance. The dependence of transfer length on gate voltage is further analyzed by using the resistance network model. The decrease of transfer length with increasing gate voltage is attributed to the decreasing ratio of contact resistor cell and channel resistor cell.3. To further investigate the underlying physics of the contact properties of a-IGZO TFTs, scanning Kelvin probe microscopy (SKPM) is utilized to separately extract the source and drain contact resistances for the first time. By measuring the surface potential of a TFT biased at a series of gate voltages, the channel resistance and source/drain resistance are calculated separately, which are found to decrease with increasing gate voltage, while the drain contact resistance is always larger than the source contact resistance.This observation indicates the resistance of bulk a-IGZO underneath the contact electrodes is not the only determinant factor of contact resistance. To understand the cause of the asymmetric S/D contact resistance, a Ti-TiOx-IGZO Schottky-like contact model is proposed, based on the fact of interface oxidation between Ti and IGZO. The asymmetry of S/D contact resistance is attributed to the difference in bias conditions of the Schottky-like junction. Therefore, the contact resistance of a-IGZO TFTs is affected by both the resistance of bulk a-IGZO underneath the contact electrodes and the resistance arising from the Schottky-like junction at the contact interface. Accordingly, two methods of improving the contact performance of the TFTs are proposed.4. In order to study the properties of the channel-gate insulator interface of the a-IGZO TFTs by low-frequency noise (LFN) characterization, a LFN measurement system focusing on the noise characterization of TFTs is set up in the first place. The LFN properties of a-IGZO TFTs annealed at three different temperatures are investigated with this system. The measured LFN is found to be 1/f type, which originates from the channel region rather than from the contacts. To obtain information about the properties of the traps near the interface, the unified model which simultaneously considers carrier number fluctuation and correlated mobility fluctuation is utilized to analyze the dependence of the normalized drain current noise power spectral density on gate voltage in a-IGZO TFTs for the first time. The annealing-temperature dependence of the border trap density and charged trap distribution is obtained. It is found that as annealing temperature increases, the border trap density decreases, while the charged traps are relatively more concentrated near the interface. The extracted border trap density and charged trap distribution, along with the PBS stability of these samples, indicates that annealing at higher temperature could reduce border traps more efficiently than the traps closer to the interface.