Data Compression Hardware System Design Based On LZW

Downhole acoustic logging data has high test accuracy,the the amount of data transmission distance, wireless transmission slow. Cause great difficulties to the storage and transmission of data, using hardware for real-time loss-less compression becomes necessary. This research project is put forward in this background.Loss-less compression format, use of statistical redundancy of data compression can be completely restored to the original data without causing any distortion, but the compression rate is a theoretical limit redundancy by statistics, is generally2:1to5:1. such methods are widely used for text data, the image data of the program and special applications (such as a fingerprint image, medical image,etc.)is compressed.Design an FPGA-based data in real-time loss-less compression system, the algorithm uses LZW algorithm. First, through the comparative analysis of the characteristics of the loss-less compression algorithm commonly used data drawn LZW algorithm in real-time, implementation complexity, the storage capacity required, the algorithm compression effect and applicable occasions have good characteristics to it as hardware the algorithms implemented. In the design of the entire hardware system, this paper also focuses on the performance of the LZW algorithm for dictionary lookup hash Hash function.Experiments show that:the shift XOR hash function hash performance is excellent, but also helps the hardware implementation. Next theoretical point of queuing theory argument the FIFO to set reasonable depth, First FIFO queuing system theory to model this paper, based on the use of basic knowledge of the birth and death process, derive mathematical formulas calculate the FIFO depth, thus calculate the FIFO depth.The hardware system design core devices FPGA, using the ALTERA Corporation Cyclone Ⅳ family EP4CE10F17C8. Constitute the required input data buffer, and the LZW algorithm2dictionary memory the FPGA chip RAM resources, and the combination of the hardware the dictionary management strategies to achieve the completion of real-time loss-less compression. This design uses QUARTUS Ⅱ software development platform for FPGA devices using Verilog schematic mixed input hierarchical description.The design is completed the data in real-time lossless compression hardware circuit, and during the hardware design before joining the Hash function LZW algorithm C language simulation, compression results encoded in line with expectations. Subsequently, the result of the coding of the hardware system using C language decoding experiments show that the data in the decoded result before the compression is completely consistent. Finally, the compression performance of the system analysis of the working of the system’s maximum clock frequency of50.14MHz, the operating current is about42mA, and the compression ratio at about50%.