Design Of Flyback LED Driver Circuit With High Power Factor And Low Ripple

The LED lighting has ushered in a new historical opportunity due to the development trend of green energy conservation in the society.As the LED is usually driven by a constant current,in order to save power and reduce the harmonic pollution,the design of the drive circuit needs to meet the requirements of high power factor?PF?.Although active PFC technology can achieve high power factor,its output terminal contains a large double-frequency ripple current,which easily causes strobe light problems and cannot be directly used as an LED driver.Therefore,it is necessary to design a circuit to reduce the ripple at the output to eliminate strobe problems effectively.In view of this,a high power factor,low ripple flyback LED driver circuit is designed in this paper,which includes power factor correction and adaptive de-ripple.The power factor correction circuit designed adopts the fixed on-time control mode and the structure design is simple.The auxiliary winding is used to sample the secondary side voltage,while the primary side feedback structure is adopted.The output current estimation circuit is used to sample the voltage of the primary resistor that is integrated.The output current-related signal is clamped to a reference value with a low-bandwidth,high-linearity error amplifier to achieve the constant-current output,As an approximately constant characteristic of the output signal V_compomp of the error amplifier in a half power frequency cycle,The constant current source charges the capacitor to generate a sawtooth signal and compares with V_compomp to generate fixed primary conduction time Ton during half of the power frequency cycle,so that the input current can follow the input voltage with an approximately sinusoidal variation,achieving a high power factor.The system circuit operates in Critical Conduction?CRM?mode,which reduces switching losses and is suitable for low power applications.As the power factor correction circuit has large power frequency ripple in the output which easily lead to strobe defects,an adaptive ripple suppression circuit is designed in the output side of the power factor correction circuit,The circuit based on the traditional LDO to sample input current changes to generate the reference voltage self-adaptively that achieve the function of suppressing the ripple.Since the reference is generated by sampling the feedback output current,it can be applied to different output currents.Compared with the traditional two-stage structure,it not only effectively reduces the output ripple and eliminates the strobe light problem,but also simplifies the design of the circuit,reduces the cost and volume,reduces the power consumption,and improves the efficiency.In this thesis,the HHNEC 0.5?m 5V/40V HVCMOS process is used to design the circuit,and the module simulation and system simulation are carried out.The control chip layout is drawn and taped out.The prototype is tested and the test result shows that the input range is 85V²65V.Inside,the output voltage range is 20V³6V,output current is 430mA,PF?0.903 under complete load,PF?0.952 under full load,THD?25%under complete load,output ripple is less than 9.8%after using ripple suppression circuit.The constant current of the system is within?3.3%.The linear adjustment rate of the system is within?4.0%,the load adjustment rate is within?1.8%,and the conversion efficiency is higher than 82.5%,meeting the design requirements.