Study On The Design Of Memristor-based D Flip-flop And Application In Scan Chain Design

With the rapid development of information technology and the expansion of data scale,big data technology has been developed rapidly in recent years.It has entered the era of big data,various types of data information have become a new treasure,which has triggered a digital revolution in many fields,such as business,economy and medicine.There are thousands of chips in these electronic systems.Sequential devices are fundamental building blocks of various digital electronic systems.As the requirement for instant data recovery after unplanned downtime is elevated increased,sequential devices are desired to be non-volatile property.In order to achieve this goal,the non-volatile memristor can be exploited to be integrated with the CMOS devices.In this work,we proposed an improved non-volatile D latch based on combining memristor and CMOS devices.It breaks down the design structure of conventional DFF and instead utilizes several transmission gates,CMOS inverter and a memristor to from a D latch.It overcomes the negative effect due to the voltage loss of the transistors and simulation results show that the proposed latch can support the memristor to switch faster between different resistance state.We also propose a non-volatile master-slave D flip-flop based on the proposed D latch.The improved circuit can save the circuit state at a faster rate under the same power supply conditions,so that the D flip-flop can support a higher frequency clocks and be suitable for high-speed electronic system.The proposed DFF takes advantage over the traditional D flip-flop and other existing memristor-based DFFs in terms of timing performance while incurring lower area overhead.Over the past few decades,it has made possible chip designs that integrate more than ten billion transistors.With the rapid development of integrated circuits(ICs)technology,the scale and complexity of IC has increase rapidly.The design of testability(DfT)has become an important part of circuit and chip design.Scan design,as the mainstream technology of DfT,has been widely used in testing.However,it does come with the extra hardware overhead and power dissipation during scan testing.With the rapid increase of IC design complexity,it is becoming the most important issue.In this work,a novel memristor-based scan flip-flop and scan hold flip-flop is proposed.The proposed designs are novel hybrid design with succinct design structure.The switching activity in the scan cells during scan mode has a significant contribution to power dissipation.The memristor-based scan cells reduce the switching activity of circuit under test(CUT),such that the power dissipation during scan mode is reduced.The new design breaks down the design structure of conventional scan cells and reduces the transistor count of the critical paths and also of the entire circuit.Thereby the entire delay and area overhead of proposed scan cells are reduced.So that the proposed scan cells have less overhead in terms of area,power consumption and delay compared to the traditional scan cells.The memristor-based scan design offers an effective solution for low power scan design.