Decoding Algorithms And Hardware Implementation Of LDPC Codes In 5G System

Low-density parity-check(LDPC)code is good channel code that closely approach the Shannon channel capacity and due to the lower decoding complexity,flexible structure,lower latency and parallel decoding,LDPC codes have been a hot topic in the channel coding field in the past decades.Now,LDPC codes have been widely used in wireless communication systems,such as WiFi,WiMAX,deep space communication and fiber optic communication and other fields.As a consequence,the LDPC codes are regarded as one of the most promising coding techniques for 5G system and finally been accepted by 3GPP as the data channel coding scheme.This paper mainly studies the characteristics,decoding algorithms and the hardware structure implementation of decoding for 5G LDPC codes.Firstly,this paper shows the configuration,parity-check matrices,code length and code rate of LDPC codes defined in 5G.Otherwise,this paper also introduces the common decoding algorithms of LDPC codes.The simulation results analysis and influence of parameters on algorithms also presented.Layered decoding scheme is given to speed up the convergence speed of decoding algorithm.Also,a layered decoding scheme based on row weights rescheduling is proposed based on the fact that there exist huge difference between the row weights in LDPC codes defined in 5G.Simulation results show that the proposed scheme can further speed up the convergence speed of decoding algorithm.Secondly,the code rate supported in 5G system is so broad.However,simulation results show that there exists huge difference between MS and BP decoding algorithm.Therefore,a hybrid decoding algorithm H-MIN was proposed.For the proposed algorithm,the check nodes was classified into two categories,the one row weights less than threshold will be updated by linearly modified algorithm and the other one will be updated by MS algorithm.Surprisely,H-MIN algorithm consumes the same storage resources as the MS algorithm and only adds a small amount of computational complexity to improve the performance greatly.Oscillation technique can effectively improve the decoding performance for low rate LDPC codes in5 G.However,the oscillation technique just simply adds two information to shock cancellation.Therefore,an improved weighted oscillation technique technique is proposed,which gives more weight to the output information of the latest iteration,thus it can further improve the decoding performance of algorithms.Simulation results show that 0.2dB decoding gain can be achieved.The hardware implementation of decoding algorithm has always been the research focus of LDPC codes.In this paper,a synchronous quasi parallel structure LDPC decoder is proposed,this decoder adopts parallel block structure with serial blocks.In this way,it does not need so many hardware resources as in full parallel architecture,and also its decoding speed is faster than that in full serial architecture.This decoder is a compromise structure between speed and hardware resources.Especially,all the codes defined in BG1 can be decoded by this decoder.The whole structure of the decoder,the principle and sequence diagram of each module are given with the formula of the decoding throughput included.Finally,this paper applies 5G-LDPC code to satellite communication,and explores the possibility of space-earth integration of mobile communication in the future.In this paper,the Suzuki channel model is used to simulate the satellite wireless channel with OFDM technology and QPSK modulation.The simulation results show that the application of LDPC code in satellite communication can significantly improve the system performance.