Design And Research Of A Dual-mode Cyclic ADC

With the continuous development of integrated circuit design and manufacturing process,from the appearance of single transistor at the beginning to the integration of gate circuit and then to today's System on a Chip(SoC)design technology,integrating hundreds of millions of transistors or even more on a small Chip has become possible.It greatly improves the reliability of the system and reduces the cost of the system.Relying on its numerous advantages,SoC has become an inevitable trend of the current technological development,and has been continuously penetrated into all walks of life to be widely used.Based on a domestic SoC chip,an ADC is designed for the system monitor.The ADC designed in this paper adopts cyclic structure,because cyclic ADC has the characteristics of small area,low power dissipation,moderate conversion accuracy and sampling speed.Traditional cyclic ADC usually only support one of the input modes of single-terminal input or differential input.However,the system monitor in this paper needs to monitor the voltage,temperature information on the chip and the analog input signals form off-chip.And these signals have both single-terminal signals and differential signals,which requires that the designed ADC can support both single-terminal and differential dual input modes.Therefore,according to the requirements of the system,in order to design a cyclic ADC that can implement both single-terminal and differential input modes,an improved double-mode RSD algorithm was proposed on the basis of the traditional RSD algorithm.Based on this algorithm,the optimization and improvement of the sampling and holding circuit switch control mode were proposed.The advantage of this control method is that it can support dual modes,and no extra clock cycle is needed for mode conversion.In the design of sampling and holding circuit and MDAC circuit,double operational amplifier structure is used to replace the traditional full-difference operational amplifier structure,which can avoid the common mode feedback circuit design and eliminate the influence of the offset error of the operational amplifier on the whole circuit.In the design of operational amplifier,an improved structure with two-stage self-compensation and gain boosted is proposed to replace the traditional miller compensation method,which can not only meet the requirements of ADC precision,but also effectively reduce the chip area occupied by it.Based on GF 28 nm standard CMOS process,the circuit design,layout drawing and post-simulation verification are completed.The post-simulation results show that the proposed cyclic ADC has a conversion speed of 200Ksps under a 5.2MHz working clock and 2.5V supply,the SNDR is 54.3dB,the ENOB is 8.7bit,the power dissipation is 4.97mW,and the layout area is 0.059mm~2.The performance fully meets the application requirements of the system monitor.