Performance Optimization And Application Of Electronic Devices Based On Novel Two-dimensional Materials

The performance of Si-based electronic devices is approaching its physical limits.With continuously shrinking the size,the short-channel effects affect the device performance degradation.Two-dimensional materials are promising in replacing Si semiconductors as new channel materials due to their uniform and atomically thin films.They have also shown great potential for many functional devices and application.Here we focused on how to optimize the electrical performance of 2D FETs and explore other possible application based on 2D in electronic logic devices.In Chapter ? and ?,we investigated the basic physical properties of two 2D semiconductor materials:TMDs and InSe.And we summarized 4 feasible solutions to optimize the electrical performance of 2D FET:1.Selecting channel materials with high mobility.2.Shrinking the device size.3.Choosing insulation materials with suitable thickness.4.Reducing contact resistance.We also introduced the device fabrication processes and measurements of 2D FET.In chapter ?,we studied the electronic properties of InSe under the environment of vacuum at low temperature and air at room temperature.We compared the device parameters among various substrates.The mobility of InSe on SiO2 substrate is 471 cm2v-1 s-1,and the on-current is about 10?A.The mobility of InSe on h-BN substrate is 931 cm2v-1s-1,and the on-current is about 20?A.The performance improvement is due to h-BN can screen carrier scattering and lower oxygen-induced degradation.We also obtained the InSe FET device with high mobility,high switching ratio,and low leak current,after concluded the performance of InSe:the mobility at room temperature reaching over 103 cm2v-1s-1,the band gap of films being about 1.4 eV,the effective electron mass being lighter(m*=0.143m0)and the relative dielectric constant being 7.In Chapter ?,we proposed three ways to improve the electrical performance of InSe FET:selecting high-K dielectric layer,shrinking the channel size of the device and reducing contact resistance.There are two processes to shrink the device size:1.Using Ag nanowires as a mask to make the channel with length below 100 nm.2.Using Ag nanowire as the electrode material of the local gate.We obtained the channel with the effective length below 100 nm,which exhibit that the local gate control switching of the channel material in metal state.We also observed that the contact resistance is the important factor to improve the on-current density.In Chapter ?,we present strategies for contact engineering.There are two processes to realize the device of InSe FET with graphene contact:1.Using PDMS dry transfer process.The electrical performance of InSe FET:the mobility being 1200 cm2v-1 s-1,the on/off ratio being over 107,the on-current density reaching 0.56 mA/pm,and the leak current being an order of nA.2.Using PVA wet transfer process.The electrical performance of InSe FET:the mobility being 877 cm2×v-1s-1,the on-current density reaching 0.83 mA/?m,and the leak current being an order of 10-1 nA.The results meet the ITRS 2017 standard for transistor device performance.In Chapter VI,we successfully demonstrated TMDs NDR device with the structure of metal/TMDs/metal.This NDR phenomenon is resulting from the thermal feedback mechanism caused by the automatic Joule heating effect.Finally,we summarized and provided outlook on the future research direction.