55nm SONOS Storage Technology And Critical Circuit Design

Over the recent years,China's imports have been dominated by semiconductor products,in which nonvolatile memories occupy a very significant share of the total market.As the most popular choice for nonvolatile memories,floating gate memories have been leading the development of memory industry for years,and SONOS memory which is based on the concept of floating gate memories is gaining favor among researchers due to its advantages over traditional memory technologiesIn SONOS memory,a thinner O-N-O three-layer structure replaces the conventional floating gate structure,which brings it further along the scaling down roadmap.The fabrication process is compatible with standard CMOS technology with only three additional masks,thus greatly reducing both production cost and the complexity involved in the manufacture process.The thinner oxide layer allows it to be operated at lower voltage,hence reducing the area of charge pumps;moreover,its program/erase characteristics of over 500K cycles and data retention of 20 years make it rather suitable for high reliability applications,including MCU,SOC,FPGA and smart cardsThis paper is part of a SONOS related research project conducted by the Key Laboratory of Microelectronic Devices&Integrated Technology of the Institute of Microelectronics,Chinese Academy of Sciences,which aims to develop a SONOS memory device based on standard 55nm CMOS technology.This paper offers a theoretical analysis of SONOS technology and delves into the discussion of some key components in the deviceWe start the paper with an introduction to the basic operations of SONOS structure,and seek to optimize the program and erase algorithms based on its target field of application.We concentrate our works on the basic storage cell of SONOS technology,measure its various electrical characteristics including P/E cycling,data retention time,fluctuation of threshold window,program/erase speed,and determine its optimal working condition based on test results.The paper then presents the architecture of SONOS memory device and its address space allocation,gives the implementation of program/erase operations,and explains the design and analysis of high voltage path.We will detail three types of core circuit structure of charge pumps,and present the circuit implementations of 4 phase clock generator,voltage divider and clock regulator.We optimize the charge pump for low output ripple,and verify its performance in a full set of PVT corners.The SONOS memory device is fabricated in 55nm CMOS technology and undergoes a series of tests.Actual test results are consistent with design specifications,lending strong support to the efficacy of the circuit structures proposed in this paper.