Design Of Signal Preprocessing Circuit For Infrared Focal Plane Array Detector

Infrared thermal imaging technology has a wide range of applications and prospects in the military,industrial and even today's civilian market.For example,the Face ID with 3D recognition based on the infrared thermal imaging is applied to the i Phone X,and it has also been considered the key to the problem of driving at night and in extreme atmospheric environments in unmanned area.The infrared focal plane detector is the most critical part of the system which converts infrared radiation into digital or analog signal so that it can be measured.In this way the image is finally generated.Compared with visible light imaging,infrared focal plane detectors usually faces the problem of nonuniformity and insufficient imaging contrast,which seriously affects the imaging results.The purpose of this thesis is to propose a signal preprocessing solution for infrared focal plane detector,namely the neural network for nonuniformity correction and histogram equalization enhancement processing based on So C FPGA platform.The advantages of each chip,including flexibility,versatility,and parallelism,are fully utilized in this program.This thesis compares and verifies the scene-based nonuniformity correction algorithm and the processing effects based on histogram equalization enhancement on the Matlab platform.The neural network for nonuniformity correction and histogram equalization enhancement are used in this thesis for signal preprocessing algorithms of infrared focal plane detector.The implementation of algorithm migration is completed on the So C FPGA platform.The infrared image sequence is used as the data source and test case suite.After image signal preprocessing,the image output to the VGA display is used as a reference for subjective evaluation.The preprocessing circuit system based on So C FPGA mainly completes the following work.With the help of Linux system mounted on the Mini SD card,the software program running on the ARM of the HPS reads a large number of picture sequence stored in the Mini SD card and performs neural network for nonuniformity correction.The FPGA part completes the acceleration of the histogram equalization enhancement.According to the So C FPGA development process,software and hardware co-design is completed.Firstly,the Qsys integration of the hardware that belongs to the FPGA is completed,including an external SDRAM controller,a frame reader which reads the image data of SDRAM and converts it to Avalon-ST stream data,histogram equalization enhancement module encapsulated with Avalon-ST interface and is also GUI configurable for operational parameters and VGA Video protocol output controller.Then,the ARM C language software which mainly accomplishes the following tasks is introduced.It reads and decodes picture sequence frames and generates virtual address of hardware resources accessed by HPS through memory-mapped way.Then,the data between HPS and FPGA is transferred and working register configuration of frame reader is done,followed by nonuniformity correction based on neural network.After the design,the waveform simulation and the subjective visual and objective histogram verification of the imaging data is performed modularly for the histogram equalization enhancement processing based on Modelsim and Matlab platforms.Finally,the entire pre-processing software and hardware integrated circuit system is realized on the So C FPGA.The comparison of specific imaging analysis shows that the expected processing effect is achieved.At the end of this thesis,we accelerate the design and verification based on the recently released Intel HLS,namely high level synthesis technology.The function of the HLS compiler tool is excavated.Based on the relevant functional instructions and interactive analysis reports,we have completed the design of component functions and test platform with seamless collaboration between software and hardware.The loop and data width is also optimized.Statistical resource consumption and verification timing have been analyzed as well.The Avalon-ST and Avalon-MM component interfaces is improved through final IP integration.Based on this brand-new design verification process,the specific implementation of the preprocessing algorithm in this thesis is introduced in detail including the environment setup,component design,verification of software and hardware models,optimization iterations and the final portable system integration.