Research On FPGA Implementation Of Neural Network Image Compression Algorithm

With the development of communications and multimedia technologies,the advent of the internet era has changed people's traditional methods of information transmission.The amount of data transmitted through networks and processed through computers,especially the amount of image data,has increased dramatically.In the case of excessive bandwidth usage and storage space occupation,researches on image lossy compression techniques are gradually developed.The application of Neural Networks(NNs)has achieved great success in the field of image processing and computer vision,especially in image recognition,semantic comprehension,image compression,image denoising and so on.However,the image compression techniques based on neural networks are mostly implemented on general-purpose microprocessors,which occupy lots of CPU resources and result in low performance and efficiency.With advances in microelectronics manufacturing processes and the development of large-scale integrated circuits,Field Programmable Gate Arrays(FPGAs)are rich in resources,flexible in configuration,and capable of parallel processing which can combine with the parallel computing characteristics of the neural network.To be an image compression hardware carrier,FPGAs can greatly improve the compression processing capability.Based on the research and analysis of the principle of neural network realization of image compression and hardware implementation of neural network,this paper designs a convolutional auto-encoder with image compression capability to overcome the deficiency of BP(Back Propagation)network,which has relatively improved the image reconstruction quality.In order to speed up the compression processing,the designed network model is implemented in the FPGA,and a periodic layer-multiplexing framework is proposed to reduce FPGA resource consumption and power consumption.In the implementation process,the paper further proposes a channel parallel method by caching input data,which avoids duplicate input of data and improves system compatibility,and proposes a parallel convolution method based on shift registers,which speeds up convolution processing.The dissertation firstly builds a Python software environment to construct a neural network model suitable for image compression and obtains expected results through network training.Then,a hardware implementation scheme is designed,using Xilinx design suite to write hardware code,carry out simulation testing,and so on.Finally,the evaluation kit of Xilinx Corporation and the windows operating system are used as test platforms for debugging and verification.To verify the performance of the neural network image compression algorithm designed in this paper,the image reconstruction quality and resource usage rate is tested.At the same time,processing speed,power consumption and computational performance comparisons are made among FPGA,CPU and GPU platform.When the FPGA system clock is 150 MHz,the experimental results of image compression and reconstruction show that the hardware framework is stable and has good image reconstruction quality.Furthermore,the hardware resource usage is less.In terms of compression processing performance and power consumption,when an RGB image with a size of 256×256 is processed,it only takes 11.23 ms and reaches a speed of 83.70 GOPS on FPGA.At the same time,the power consumption of the FPGA is much lower than that of the CPU and the GPU,and the computing performance per watt is significantly better than these two platforms.This indicates that FPGA has great performance advantages as the realization platform of neural network image compression algorithm,and also indicates that the design of this paper has a great application prospect in the field of digital signal processing.