A Study Of Interfacial Properties Of High-k/InGaAs MOS Capacitor

Over the past four decades,the performance of Si-based complementary metal oxide semiconductors has tended to limit as the device size continues to scale down.In order to continue Moore's law,high-k gate dielectric have replaced SiO₂ as the new gate oxide layer.While III-V compound semiconductor InGaAs has become the new channel material due to its high carrier mobility and low leakage characteristics after CMOS technology advances to 10 nm node.However,there is a high interface state density between the high k/InGaAs interface,especially when the thickness of the oxide layer reaches deep sub-micron level,Fermi level pinning occurs and device performance gets worse.Therefore,finding the surface passivation methods and high quality gate dielectric to improve the interface quality has become the biggest challenge at present.In order to achieve high performance InGaAs MOSFETs,this paper focuses on the promotion of high-k gate dielectric and passivation layer on the electrical properties and interface characteristics of InGaAs devices.A new gate structure has been designed to reduce the interface state density to obtain a higher device performance.In this study,the process of metal/high-k/InGaAs MOS capacitor fabrication is first introduced.Then we analyze the ideal capacitance-voltage?C-V?characteristic of the MOS capacitor and extract the important physical parameters.Then the charges in the high-k/InGaAs MOS system are introduced,and the effect on the device characteristics are studied.At the same time,two methods for extracting interface states density are introduced,including Terman method and conductance method.Finally,leakage current transmission mechanisms are described in detail,including direct tunneling?DT?,Fowler-Nordheim tunneling,Schottky transmission,Frenkel-Poole emission,and space charge limit conduction mechanism,and their judgment methods are introduced.The ZrO₂/In_0.2Ga_0.8As MOS capacitor was fabricated experimentally.Firstly,the cause of the interface states of high-k/InGaAs and the reasons for the Fermi-level pinning effect are analyzed theoretically.From the experimental results,it was found that the ZrO₂/In_0.2Ga_0.8As MOS capacitor structure obtained a higher k value,and the high dielectric constant ZrO₂ has great potential for future III-V MOSFETs,which can further reduce the device size.At the same time,there is a large interface state between ZrO₂/In_0.2Ga_0.8As which lead to the Fermi level pinning and high gate leakage currrent.XPS test results show that the main reasons for the interface state are the low-k oxides and dangling bonds between ZrO₂/In_0.2Ga_0.8A interface,including In₂O,In₂O₃,Ga₂O,Ga₂O₃,In_xGa_yO_z,As₂O and As-As bonds,which lead to poor interface properties,resulting in lower capacitance values in the accumulation region,a more gradual C-V curve and Fermi level pinning effects.The main mechanisms for gate leakage current are Schottky emission and space charge limit conduction mechanisms,and the Schottky barrier height and trap level depth?E_c-E_t?between ZrO₂/In_0.2Ga_0.8As are extracted.Aiming at the conclusions of the experimental analysis,a interface passivation method was proposed,namely adding ZnO passivation layer between ZrO₂/In_0.2Ga_0.8As to carry out the next experiment.According to the research results of the interface characteristics of ZrO₂/In_0.2Ga_0.8As MOS capacitors,ZrO₂/ZnO/In_0.2Ga_0.8As MOS capacitor was experimentally fabricated using a zinc oxide passivation layer.A smooth interface between ZrO₂ and p-In_0.2Ga_0.8As was observed through the TEM test,and the boundaries between layers were distinct.The C-V test results show that after adding ZnO IPL,the value of accumulation capacitance is larger,the frequency dispersion in the accumulation region is suppressed,the interface state density is lower,and the Fermi level effect pinning has improved.The dominant gate leakage mechanism of the ZrO₂/ZnO/In_0.2Ga_0.8As MOS capacitor was obtained from a variable temperature I-V test.The conduction band and valence band offset of the two gate structures with and without ZnO IPL were calculated by XPS spectra.The insertion of the ZnO passivation layer raises the barrier height between the oxide layer and InGaAs,making it more difficult for carriers to cross the oxide layer to the metal side,resulting in the suppression of leakage currents.At the same time,the ZnO IPL suppresses the interface traps,reducing the probability of traps trapped by carriers and undergoing transitions under a small energy,and suppresses the conduction of gate leakage current,resulting in a lower power consumption and a better performance.