Parametric Design And Verification Of X-DSP Vector Processer Unit

Different design has different demands on performance,area and power consumption of the DSP core.It is important to design a flexible and efficient DSP IP core in practice.X-DSP is a general 32-bit high-performance multi-core DSP that was developed by us independently,whose frequency and single precision peak performance are 1GHz and 200 GFlops separately.X-DSP adopts 11 VLIW and SIMD structure,and uses 16 homogeneous computing elements to conduct large-scale data parallel processing in the vector arithmetic unit.In this paper,with the development of X-DSP and IP core,we have done parameterized design and verification towards vector operation components to meet the needs of various purposes to increase the kernel flexibility.The main contents are as follows:1.The internal structure parametric design of vector process unit was completed in this thesis.We analysed the layout of 16 isomorphism vector processing element in vector arithmetic unit,and got the parameterized layout as well as global signals.At the same time,the macro definition method was adopted to conduct parametric design on the vector instructions decoding unit.Especially for shuffle and VRDC module,different invoked module structures were designed in various parameters conditions.2.The parametric design of the data interaction pathway between vector processing unit and other nuclear components was completed in this thesis.For the SVB and SVR which interact with scalar process elements,SVB was made parametric design of the control system and data signals,while SVR conducted parametric design of the sharing body and the interconnection between share body and vector unit respectively.What's more,since there are many vector data access memory pathways between VPU and AM,we also have completed the corresponding parametric design for them.3.The fully functional verification of the completion circuit with parametric design had made in this thesis.First,we taken use of auto check to check the code;Second,we adapt comparison verification strategy,which is based on the golden model,to guarantee the result accuracy.Further,we also had accomplished the verification of the basic function points,global signals,instruction integrated signals,etc;Third,we adapt the similar checking tool—ATEC to make the equal verification between RTL design and C language gold models,to ensure the correctness the hardware design function;Forth,we collected the function coverage information to accelerate the convergence of functional verification.Finally,we used the 45 nm library to synthesize the code,and the synthesize results show that for the design accords with expectations,the area of 8PE is 58.79%of 16PE;the area of 4PE is 38% of 16 PE.For the power consumption,the consumption of 8PE is 58.6% of 16 PE,and the consumption of 4PE is 39.3% of 16 PE.