Study On E_band Frequency Synthesizer

Considering the current application background of 5G communication,the world radiocommunication Conference on 5G communication band do re division of E_band,which is divided into 66 to 76 GHz,and 81 to 86 GHz.This paper designed the circuit of PLL,which is the key part in communication chip.The design of the main frequency band is from 66 to 76 GHz.Firstly,this paper analyzes the architecture of the charge pump PLL system from the point of view of system analysis.Through the analysis of the s domain model of each part in the PLL,the transfer function of the system is determined.Then,MATLAB is used to simulate the loop,and the parameters are adjusted repeatedly.Secondly,the design of each circuit in the phase locked loop is summarized.From the selection of the structure to the optimization of the parameters,as well as the final layout.Among them,the design of QVCO is put forward by using buffer feedback method to optimize the phase noise,this method compared to before the direct capacitive feedback approach can not only reduce the load capacitance but also improve phase noise.As for the divider in the first stage,considering the high operation speed,the circuit uses ILFD as the first stage of the divider,and by adding switch-capacitor bank to adjust self resonant frequency to improve locking range.Then using 3 CML frequency divider after ILFD,the frequency will be divided into low frequency.After the CML,the MMD is used to divider the frequency to the input of PFD.For the charge pump,which uses a voltage comparator feedback structure,the current has low mismatch.Two order filter for loop filter.Thirdly,the design of the chip was taped out in TSMC65 nm production process,and tested by ligation probe method.The measure results show that the operating frequency of VCO can be caver from 68.1 to 73.8GHz,and the phase noise can reach-95dBc@1MHz.The locking phase of-93dBc@1MHz can reach in PLL.And the total power consumption is 37.1mW.