Optimization Techniques For Quick Fault Detection In Post Silicon Validation

Semiconductor silicon chips are the essential foundation for the operation of every single electronic device,pervasively integrated into daily life.From the perspective of silicon designers,the silicon chips need to be validated and debugged thoroughly before massive production so that they can be guaranteed to be secure and reliable.Post silicon validation is a crucial technique in silicon validation procedure and dominates the overall time cost of silicon design.Post silicon validation suffers from the long validation period because it is applied on the prototype silicon and lacks efficient solutions to observe the faults.Moore's laws and Dennard Scaling indicate the state-of-the-art silicon chips are getting more and more complex,especially multiprocessor system-on-chip and exacerbate the difficulty in the post silicon validation.Meanwhile,the iterative rate of silicon chip is increasing.Therefore,how to conduct post silicon validation in a quick and efficient approach is the most important challenge in silicon validation field.This paper targets on the long validation period and makes three contributions as follows:First,this paper proposes optimization techniques for quick fault detection in post silicon validation based on LLVM(Low level virtual machine)compiler infrastructure.After analyzing the overall procedure of post silicon validation,we observe that long detection latency is the bottleneck of post silicon validation and limits the optimization of silicon validation.By applying the typical fault-tolerant algorithms,we present a fault detection model to bound the detection latency and this optimized model is implemented in LLVM compiler infrastructure and is extensible and therefore is easily applied to chips of diverse architectures.Our model realizes the systematization and automation in post silicon validation.Second,we design a fault latency detection framework based on gem5 simulator.We observe that activating the faults on the silicon chips in an extreme physical way is infeasible and fault latency is unable to be measured in hardware environment,so we choose the gem5 simulator and on this platform we model real bugs from state-of-the-art commercial silicon chips and design an unprecedented way to measure the fault latency after activating bugs.The selection of candidate fault instruction and the injection of candidate fault instruction make the framework extensible.Finally,we conduct a large scale evaluation to access the effectiveness of our proposed software-implemented fault detection optimization model.The result shows that the fault latency of our proposed model can be bounded to several thousand cycle and the coverage can be improved by 2X on average,which helps the fault localization in the procedure of post silicon validation.